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Searched refs:S5_WRITEDISABLE_MASK (Results 1 – 4 of 4) sorted by relevance

/third_party/mesa3d/src/mesa/drivers/dri/i915/
Dintel_reg.h144 #define S5_WRITEDISABLE_MASK (0xf<<28) macro
Di915_state.c695 GLuint tmp = i915->state.Ctx[I915_CTXREG_LIS5] & ~S5_WRITEDISABLE_MASK; in i915ColorMask()
/third_party/mesa3d/src/gallium/drivers/i915/
Di915_state_emit.c125 uint32_t writemask = imm & S5_WRITEDISABLE_MASK; in emit_immediate_s5()
126 imm &= ~S5_WRITEDISABLE_MASK; in emit_immediate_s5()
Di915_reg.h376 #define S5_WRITEDISABLE_MASK (0xf << 28) macro