| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVFrameLowering.cpp | 117 Register SPReg = getSPReg(STI); in emitPrologue() local
137 if (STI.isRegisterReservedByUser(SPReg)) in emitPrologue()
147 adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup); in emitPrologue()
181 adjustReg(MBB, MBBI, DL, FPReg, SPReg, in emitPrologue()
196 adjustReg(MBB, MBBI, DL, SPReg, SPReg, -SecondSPAdjustAmount, in emitPrologue()
218 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg) in emitPrologue()
219 .addReg(SPReg) in emitPrologue()
226 .addReg(SPReg) in emitPrologue()
228 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg) in emitPrologue()
238 .addReg(SPReg) in emitPrologue()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFrameLowering.cpp | 174 unsigned SPReg = WebAssembly::SP32; in emitPrologue() local
176 SPReg = MRI.createVirtualRegister(PtrRC); in emitPrologue()
180 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::GLOBAL_GET_I32), SPReg) in emitPrologue()
189 .addReg(SPReg); in emitPrologue()
198 .addReg(SPReg) in emitPrologue()
240 unsigned SPReg = 0; in emitEpilogue() local
243 SPReg = FI->getBasePointerVreg(); in emitEpilogue()
252 SPReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue()
253 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::ADD_I32), SPReg) in emitEpilogue()
257 SPReg = hasFP(MF) ? WebAssembly::FP32 : WebAssembly::SP32; in emitEpilogue()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 831 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1; in emitPrologue() local
983 .addReg(SPReg); in emitPrologue()
1012 .addReg(SPReg); in emitPrologue()
1017 .addReg(SPReg); in emitPrologue()
1022 .addReg(SPReg); in emitPrologue()
1029 .addReg(SPReg); in emitPrologue()
1037 .addReg(SPReg); in emitPrologue()
1050 .addReg(SPReg) in emitPrologue()
1051 .addReg(SPReg); in emitPrologue()
1062 .addReg(SPReg) in emitPrologue()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 136 unsigned SPReg = MI.getOperand(0).getReg(); in sandboxLoadStoreStackChange() local
137 assert((Mips::SP == SPReg) && "Unexpected stack-pointer register."); in sandboxLoadStoreStackChange()
138 emitMask(SPReg, LoadStoreStackMaskReg, STI); in sandboxLoadStoreStackChange()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFrameLowering.cpp | 95 unsigned ScratchRsrcReg, unsigned SPReg, int FI) { in buildPrologSpill() argument
109 .addReg(SPReg) in buildPrologSpill()
130 .addReg(SPReg) in buildPrologSpill()
143 unsigned ScratchRsrcReg, unsigned SPReg, int FI) { in buildEpilogReload() argument
156 .addReg(SPReg) in buildEpilogReload()
177 .addReg(SPReg) in buildEpilogReload()
493 unsigned SPReg = MFI->getStackPtrOffsetReg(); in emitEntryFunctionPrologue() local
494 assert(SPReg != AMDGPU::SP_REG); in emitEntryFunctionPrologue()
522 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), SPReg) in emitEntryFunctionPrologue()
525 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), SPReg) in emitEntryFunctionPrologue()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FrameLowering.h | 103 int FI, unsigned &SPReg) const;
105 int FI, unsigned &SPReg, int Adjustment) const;
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| D | X86RetpolineThunks.cpp | 232 const unsigned SPReg = Is64Bit ? X86::RSP : X86::ESP; in insertRegReturnAddrClobber() local
233 addRegOffset(BuildMI(&MBB, DebugLoc(), TII->get(MovOpc)), SPReg, false, 0) in insertRegReturnAddrClobber()
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| D | X86CallLowering.cpp | 111 Register SPReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
112 MIRBuilder.buildCopy(SPReg, STI.getRegisterInfo()->getStackRegister()); in getStackAddress()
118 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
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| D | X86FrameLowering.cpp | 1544 unsigned SPReg; in getPSPSlotOffsetFromSP() local
1545 int Offset = getFrameIndexReferencePreferSP(MF, Info.PSPSymFrameIdx, SPReg, in getPSPSlotOffsetFromSP()
1547 assert(Offset >= 0 && SPReg == TRI->getStackRegister()); in getPSPSlotOffsetFromSP()
2666 unsigned ScratchReg, SPReg, PReg, SPLimitOffset; in adjustForHiPEPrologue() local
2670 SPReg = X86::RSP; in adjustForHiPEPrologue()
2676 SPReg = X86::ESP; in adjustForHiPEPrologue()
2689 SPReg, false, -MaxStack); in adjustForHiPEPrologue()
2699 SPReg, false, -MaxStack); in adjustForHiPEPrologue()
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| D | X86ISelLowering.cpp | 23066 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); in LowerDYNAMIC_STACKALLOC() local
23067 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" in LowerDYNAMIC_STACKALLOC()
23070 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); in LowerDYNAMIC_STACKALLOC()
23079 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Result); // Output chain in LowerDYNAMIC_STACKALLOC()
23105 Register SPReg = RegInfo->getStackRegister(); in LowerDYNAMIC_STACKALLOC() local
23106 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy); in LowerDYNAMIC_STACKALLOC()
23112 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP); in LowerDYNAMIC_STACKALLOC()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 102 Register SPReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
103 MIRBuilder.buildCopy(SPReg, Register(ARM::SP)); in getStackAddress()
109 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsCallLowering.cpp | 294 Register SPReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
295 MIRBuilder.buildCopy(SPReg, Register(Mips::SP)); in getStackAddress()
302 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallLowering.cpp | 156 Register SPReg = MRI.createGenericVirtualRegister(p0); in getStackAddress() local
157 MIRBuilder.buildCopy(SPReg, Register(AArch64::SP)); in getStackAddress()
163 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.cpp | 1023 unsigned SPReg = getStackPointerRegisterToSaveRestore(); in LowerDYNAMIC_STACKALLOC() local
1026 SDValue StackPointer = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i32); in LowerDYNAMIC_STACKALLOC()
1046 SDValue CopyChain = DAG.getCopyToReg(Chain, DL, SPReg, Sub); in LowerDYNAMIC_STACKALLOC()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 11131 int SPReg = tryParseRegister(); in parseDirectiveSetFP() local
11132 if (check(SPReg == -1, SPRegLoc, "stack pointer register expected") || in parseDirectiveSetFP()
11133 check(SPReg != ARM::SP && SPReg != UC.getFPReg(), SPRegLoc, in parseDirectiveSetFP()
11163 static_cast<unsigned>(SPReg), Offset); in parseDirectiveSetFP()
11453 int SPReg = tryParseRegister(); in parseDirectiveMovSP() local
11454 if (SPReg == -1) in parseDirectiveMovSP()
11456 if (SPReg == ARM::SP || SPReg == ARM::PC) in parseDirectiveMovSP()
11481 getTargetStreamer().emitMovSP(SPReg, Offset); in parseDirectiveMovSP()
11482 UC.saveFPReg(SPReg); in parseDirectiveMovSP()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 1586 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); in ExpandDYNAMIC_STACKALLOC() local
1587 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" in ExpandDYNAMIC_STACKALLOC()
1601 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); in ExpandDYNAMIC_STACKALLOC()
1610 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain in ExpandDYNAMIC_STACKALLOC()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 2593 unsigned SPReg = SP::O6; in LowerDYNAMIC_STACKALLOC() local
2594 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); in LowerDYNAMIC_STACKALLOC()
2596 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain in LowerDYNAMIC_STACKALLOC()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 4264 Register SPReg = TLI.getStackPointerRegisterToSaveRestore(); in lowerDynStackAlloc() local
4265 auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg); in lowerDynStackAlloc()
4280 MIRBuilder.buildCopy(SPReg, SPTmp); in lowerDynStackAlloc()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 3384 unsigned SPReg = getStackPointerRegisterToSaveRestore(); in lowerDYNAMIC_STACKALLOC() local
3388 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64); in lowerDYNAMIC_STACKALLOC()
3404 Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP); in lowerDYNAMIC_STACKALLOC()
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