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Searched refs:ST0 (Results 1 – 25 of 30) sorted by relevance

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/third_party/mesa3d/src/mesa/x86/
Dx86_xform4.S120 FADDP( ST0, ST(7) ) /* F2 F1 F3 F7 F6 F5 F4 */
122 FADDP( ST0, ST(5) ) /* F2 F3 F7 F6 F5 F4 */
123 FADDP( ST0, ST(3) ) /* F3 F7 F6 F5 F4 */
124 FADDP( ST0, ST(1) ) /* F7 F6 F5 F4 */
136 FADDP( ST0, ST(7) ) /* F2 F1 F3 F7 F6 F5 F4 */
138 FADDP( ST0, ST(5) ) /* F2 F3 F7 F6 F5 F4 */
139 FADDP( ST0, ST(3) ) /* F3 F7 F6 F5 F4 */
140 FADDP( ST0, ST(1) ) /* F7 F6 F5 F4 */
152 FADDP( ST0, ST(7) ) /* F2 F1 F3 F7 F6 F5 F4 */
154 FADDP( ST0, ST(5) ) /* F2 F3 F7 F6 F5 F4 */
[all …]
Dx86_xform3.S120 FADDP( ST0, ST(7) ) /* F2 F1 F3 F7 F6 F5 F4 */
122 FADDP( ST0, ST(5) ) /* F2 F3 F7 F6 F5 F4 */
123 FADDP( ST0, ST(3) ) /* F3 F7 F6 F5 F4 */
124 FADDP( ST0, ST(1) ) /* F7 F6 F5 F4 */
136 FADDP( ST0, ST(7) ) /* F2 F1 F3 F7 F6 F5 F4 */
138 FADDP( ST0, ST(5) ) /* F2 F3 F7 F6 F5 F4 */
139 FADDP( ST0, ST(3) ) /* F3 F7 F6 F5 F4 */
140 FADDP( ST0, ST(1) ) /* F7 F6 F5 F4 */
223 FADDP( ST0, ST(4) ) /* F1 F2 F5 F4 */
224 FADDP( ST0, ST(2) ) /* F2 F5 F4 */
[all …]
Dx86_xform2.S120 FADDP( ST0, ST(7) ) /* F2 F1 F3 F7 F6 F5 F4 */
122 FADDP( ST0, ST(5) ) /* F2 F3 F7 F6 F5 F4 */
123 FADDP( ST0, ST(3) ) /* F3 F7 F6 F5 F4 */
124 FADDP( ST0, ST(1) ) /* F7 F6 F5 F4 */
273 FADDP( ST0, ST(5) ) /* F1 F2 F6 F5 F4 */
274 FADDP( ST0, ST(3) ) /* F2 F6 F5 F4 */
275 FADDP( ST0, ST(1) ) /* F6 F5 F4 */
353 FADDP( ST0, ST(2) ) /* F4 F5 */
421 FADDP( ST0, ST(3) ) /* F1 F5 F4 */
422 FADDP( ST0, ST(1) ) /* F5 F4 */
[all …]
Dx86_cliptest.S229 FMUL2( ST(1), ST0 )
232 FMUL2( ST(2), ST0 )
235 FMUL2( ST(3), ST0 )
Dassyntax.h210 #define ST0 %st(0) macro
212 #define ST0 %st macro
891 #define ST0 st0 macro
/third_party/ffmpeg/libavcodec/arm/
Dmlpdsp_armv5te.S38 ST0 .req v5 label
192 SHIFT .req ST0
225 mov SHIFT, ST0
236 ldr ST0, [PSAMP]
239 and ST0, ST0, MASK
241 str ST0, [PST, #-4]!
242 str ST0, [PST, #4 * (MAX_BLOCKSIZE + MAX_FIR_ORDER)]
243 str ST0, [PSAMP], #4 * MAX_CHANNELS
408 ldm v1, {ST0,ST1,I,PSAMP}
411 movs ST2, ST0, lsl #29 // shift is in range 0-15; we want to special-case 0 and 8
[all …]
/third_party/libunwind/src/x86/
Dinit.h44 c->dwarf.loc[ST0] = DWARF_REG_LOC (&c->dwarf, UNW_X86_ST0); in common_init()
45 for (i = ST0 + 1; i < DWARF_NUM_PRESERVED_REGS; ++i) in common_init()
Dunwind_i.h47 #define ST0 11 macro
DGget_save_loc.c50 case UNW_X86_ST0: loc = c->dwarf.loc[ST0]; break; in unw_get_save_loc()
DGregs.c130 loc = c->dwarf.loc[ST0]; in tdep_access_fpreg()
DGos-freebsd.c141 c->dwarf.loc[ST0] = DWARF_NULL_LOC; in x86_handle_signal_frame()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86FloatingPoint.cpp205 return StackTop - 1 - getSlot(RegNo) + X86::ST0; in getSTReg()
852 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0); in popStackAfter()
1111 MachineOperand::CreateReg(X86::ST0, /*isDef*/ true, /*isImp*/ true)); in handleZeroArgFP()
1157 MachineOperand::CreateReg(X86::ST0, /*isDef*/ false, /*isImp*/ true)); in handleOneArgFP()
1647 Op.setReg(X86::ST0 + FPReg); in handleSpecialFP()
DX86Instr3DNow.td78 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in
DX86RegisterInfo.cpp573 Reserved.set(X86::ST0 + n); in getReservedRegs()
DX86RegisterInfo.td191 // MMX Registers. These are actually aliased to ST0 .. ST7
282 def ST0 : X86Reg<"st", 0>, DwarfRegNum<[33, 12, 11]>;
DX86InstrControl.td19 // The X86retflag return instructions are variadic because we may add ST0 and
DX86InstrFPStack.td677 let Uses = [ST0, FPCW] in {
686 let Defs = [EFLAGS, FPSW], Uses = [ST0, FPCW] in {
DX86InstrMMX.td156 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in
/third_party/boost/libs/context/doc/
Drationale.qbk115 "The MMX and floating-point stack registers (MM0-MM7/ST0-ST7) are preserved across
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86ATTInstPrinter.cpp484 if (Reg == X86::ST0) in printSTiRegOperand()
DX86IntelInstPrinter.cpp441 if (Reg == X86::ST0) in printSTiRegOperand()
DX86MCTargetDesc.cpp116 {codeview::RegisterId::ST0, X86::FP0}, in initLLVMToSEHAndCVRegMapping()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenRegisterInfo.inc155 ST0 = 135,
1271 { X86::ST0 },
2396 X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7,
2748 { 33U, X86::ST0 },
2801 { 12U, X86::ST0 },
2846 { 11U, X86::ST0 },
2915 { 33U, X86::ST0 },
2968 { 12U, X86::ST0 },
3013 { 11U, X86::ST0 },
3091 { X86::ST0, 33U },
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/DebugInfo/CodeView/
DCodeViewRegisters.def123 CV_REGISTER(ST0, 128)
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/
DX86Disassembler.cpp2206 mcInst.addOperand(MCOperand::createReg(X86::ST0 + stackPos)); in translateFPRegister()

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