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/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceTargetLoweringX8632.h348 void lowerCaseCluster(const CaseCluster &Case, Operand *Src0, bool DoneCmp,
399 Operand *legalizeSrc0ForCmp(Operand *Src0, Operand *Src1);
444 void _adc(Variable *Dest, Operand *Src0) { in _adc() argument
445 Context.insert<Insts::Adc>(Dest, Src0); in _adc()
450 void _add(Variable *Dest, Operand *Src0) { in _add() argument
451 Context.insert<Insts::Add>(Dest, Src0); in _add()
456 void _addps(Variable *Dest, Operand *Src0) { in _addps() argument
457 Context.insert<Insts::Addps>(Dest, Src0); in _addps()
459 void _addss(Variable *Dest, Operand *Src0) { in _addss() argument
460 Context.insert<Insts::Addss>(Dest, Src0); in _addss()
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DIceTargetLoweringX8664.h344 void lowerCaseCluster(const CaseCluster &Case, Operand *Src0, bool DoneCmp,
395 Operand *legalizeSrc0ForCmp(Operand *Src0, Operand *Src1);
440 void _adc(Variable *Dest, Operand *Src0) { in _adc() argument
441 Context.insert<Insts::Adc>(Dest, Src0); in _adc()
446 void _add(Variable *Dest, Operand *Src0) { in _add() argument
447 Context.insert<Insts::Add>(Dest, Src0); in _add()
452 void _addps(Variable *Dest, Operand *Src0) { in _addps() argument
453 Context.insert<Insts::Addps>(Dest, Src0); in _addps()
455 void _addss(Variable *Dest, Operand *Src0) { in _addss() argument
456 Context.insert<Insts::Addss>(Dest, Src0); in _addss()
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DIceTargetLoweringMIPS32.h166 void _add(Variable *Dest, Variable *Src0, Variable *Src1) { in _add() argument
167 Context.insert<InstMIPS32Add>(Dest, Src0, Src1); in _add()
170 void _addu(Variable *Dest, Variable *Src0, Variable *Src1) { in _addu() argument
171 Context.insert<InstMIPS32Addu>(Dest, Src0, Src1); in _addu()
174 void _and(Variable *Dest, Variable *Src0, Variable *Src1) { in _and() argument
175 Context.insert<InstMIPS32And>(Dest, Src0, Src1); in _and()
188 void _br(CfgNode *TargetTrue, CfgNode *TargetFalse, Operand *Src0, in _br() argument
190 Context.insert<InstMIPS32Br>(TargetTrue, TargetFalse, Src0, Src1, in _br()
194 void _br(CfgNode *TargetTrue, CfgNode *TargetFalse, Operand *Src0, in _br() argument
196 Context.insert<InstMIPS32Br>(TargetTrue, TargetFalse, Src0, Condition); in _br()
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DIceTargetLoweringARM32.h212 Operand *Src0, Operand *Src1);
252 Operand *Src0, Operand *Src1);
253 CondWhenTrue lowerInt32IcmpCond(InstIcmp::ICond Condition, Operand *Src0,
255 CondWhenTrue lowerInt64IcmpCond(InstIcmp::ICond Condition, Operand *Src0,
257 CondWhenTrue lowerIcmpCond(InstIcmp::ICond Condition, Operand *Src0,
326 void _add(Variable *Dest, Variable *Src0, Operand *Src1,
328 Context.insert<InstARM32Add>(Dest, Src0, Src1, Pred);
330 void _adds(Variable *Dest, Variable *Src0, Operand *Src1,
333 Context.insert<InstARM32Add>(Dest, Src0, Src1, Pred, SetFlags);
338 void _adc(Variable *Dest, Variable *Src0, Operand *Src1,
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DIceTargetLoweringX8632.cpp657 Operand *&Src0, Operand *&Src1) { in canFoldLoadIntoBinaryInst() argument
658 if (Src0 == LoadDest && Src1 != LoadDest) { in canFoldLoadIntoBinaryInst()
659 Src0 = LoadSrc; in canFoldLoadIntoBinaryInst()
662 if (Src0 != LoadDest && Src1 == LoadDest) { in canFoldLoadIntoBinaryInst()
710 Operand *Src0 = Arith->getSrc(0); in doLoadOpt() local
712 if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1)) { in doLoadOpt()
714 Arith->getDest(), Src0, Src1); in doLoadOpt()
717 Operand *Src0 = Icmp->getSrc(0); in doLoadOpt() local
719 if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1)) { in doLoadOpt()
721 Icmp->getDest(), Src0, Src1); in doLoadOpt()
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DIceTargetLoweringX8664.cpp666 Operand *&Src0, Operand *&Src1) { in canFoldLoadIntoBinaryInst() argument
667 if (Src0 == LoadDest && Src1 != LoadDest) { in canFoldLoadIntoBinaryInst()
668 Src0 = LoadSrc; in canFoldLoadIntoBinaryInst()
671 if (Src0 != LoadDest && Src1 == LoadDest) { in canFoldLoadIntoBinaryInst()
720 Operand *Src0 = Arith->getSrc(0); in doLoadOpt() local
722 if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1)) { in doLoadOpt()
724 Arith->getDest(), Src0, Src1); in doLoadOpt()
727 Operand *Src0 = Icmp->getSrc(0); in doLoadOpt() local
729 if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1)) { in doLoadOpt()
731 Icmp->getDest(), Src0, Src1); in doLoadOpt()
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DIceTargetLoweringARM32.cpp531 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() local
537 Context.insert<InstCast>(CastKind, Src0_32, Src0); in genTargetHelperCallFor()
538 Src0 = Src0_32; in genTargetHelperCallFor()
564 assert(Src0->getType() == IceType_i32); in genTargetHelperCallFor()
565 Call->addArg(Src0); in genTargetHelperCallFor()
592 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() local
594 const Type SrcTy = Src0->getType(); in genTargetHelperCallFor()
616 Call->addArg(Src0); in genTargetHelperCallFor()
635 Call->addArg(Src0); in genTargetHelperCallFor()
663 Context.insert<InstCast>(InstCast::Zext, Src0AsI32, Src0); in genTargetHelperCallFor()
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DIceTargetLoweringMIPS32.cpp304 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() local
314 Context.insert<InstExtractElement>(Op0, Src0, Index); in genTargetHelperCallFor()
331 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() local
333 const Type SrcType = Src0->getType(); in genTargetHelperCallFor()
342 Context.insert<InstExtractElement>(Op0, Src0, Index); in genTargetHelperCallFor()
419 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() local
420 const Type SrcTy = Src0->getType(); in genTargetHelperCallFor()
433 Context.insert<InstExtractElement>(Op, Src0, Index); in genTargetHelperCallFor()
473 Call->addArg(Src0); in genTargetHelperCallFor()
502 Call->addArg(Src0); in genTargetHelperCallFor()
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DIceInstARM32.h745 Variable *Src0, Operand *Src1,
749 InstARM32ThreeAddrGPR(Func, Dest, Src0, Src1, Predicate, SetFlags);
770 InstARM32ThreeAddrGPR(Cfg *Func, Variable *Dest, Variable *Src0, in InstARM32ThreeAddrGPR() argument
774 addSource(Src0); in InstARM32ThreeAddrGPR()
795 static InstARM32ThreeAddrFP *create(Cfg *Func, Variable *Dest, Variable *Src0, in create() argument
798 InstARM32ThreeAddrFP(Func, Dest, Src0, Src1); in create()
821 InstARM32ThreeAddrFP(Cfg *Func, Variable *Dest, Variable *Src0, Operand *Src1) in InstARM32ThreeAddrFP() argument
823 addSource(Src0); in InstARM32ThreeAddrFP()
846 Variable *Src0, Variable *Src1) { in create() argument
848 InstARM32ThreeAddrSignAwareFP(Func, Dest, Src0, Src1); in create()
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DIceInstMIPS32.h409 Variable *Src0) { in create() argument
411 InstMIPS32TwoAddrFPR(Func, Dest, Src0); in create()
436 InstMIPS32TwoAddrFPR(Cfg *Func, Variable *Dest, Variable *Src0) in InstMIPS32TwoAddrFPR() argument
438 addSource(Src0); in InstMIPS32TwoAddrFPR()
453 Variable *Src0) { in create() argument
455 InstMIPS32TwoAddrGPR(Func, Dest, Src0); in create()
480 InstMIPS32TwoAddrGPR(Cfg *Func, Variable *Dest, Variable *Src0) in InstMIPS32TwoAddrGPR() argument
482 addSource(Src0); in InstMIPS32TwoAddrGPR()
500 Variable *Src0, Variable *Src1) { in create() argument
502 InstMIPS32ThreeAddrFPR(Func, Dest, Src0, Src1); in create()
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DIceInstARM32.cpp1163 const Operand *Src0 = getSrc(0); in emitIAS() local
1165 Type SrcTy = Src0->getType(); in emitIAS()
1179 Asm->vqmovn2(typeElementType(DestTy), Dest, Src0, Src1, Unsigned, in emitIAS()
1185 Asm->vqmovn2(typeElementType(DestTy), Dest, Src0, Src1, Unsigned, in emitIAS()
1191 Asm->vqmovn2(typeElementType(DestTy), Dest, Src0, Src1, Unsigned, in emitIAS()
1202 const Operand *Src0 = getSrc(0); in emitIAS() local
1203 Type SrcTy = Src0->getType(); in emitIAS()
1228 const Operand *Src0 = getSrc(0); in emitIAS() local
1230 Type SrcTy = Src0->getType(); in emitIAS()
1236 Asm->vmlap(typeElementType(SrcTy), Dest, Src0, Src1); in emitIAS()
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DIceTargetLowering.h460 Operand *Src0, Operand *Src1);
523 auto *Src0 = thunk0(); in applyToThunkedArgs() local
524 return insertScalarInstruction(Res, Src0); in applyToThunkedArgs()
532 auto *Src0 = thunk0(); in applyToThunkedArgs() local
534 return insertScalarInstruction(Res, Src0, Src1); in applyToThunkedArgs()
542 auto *Src0 = thunk0(); in applyToThunkedArgs() local
545 return insertScalarInstruction(Res, Src0, Src1, Src2); in applyToThunkedArgs()
DIceTargetLoweringARM32.def27 // vcCC0_V Cmp0, Src0, Src1 /* only if CC0_V != none */
28 // vcCC1_V Cmp1, Src1, Src0 /* only if CC1_V != none */
32 // If INV_V = true, then Src0 and Src1 should be swapped.
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/unittest/AssemblerX8664/
DControlFlow.cpp17 #define TestJ(C, Near, Dest, Src0, Value0, Src1, Value1) \ in TEST_F() argument
20 "(" #C ", " #Near ", " #Dest ", " #Src0 ", " #Value0 ", " #Src1 \ in TEST_F()
24 __ mov(IceType_i32, Encoded_GPR_##Src0(), Immediate(Value0)); \ in TEST_F()
27 __ cmp(IceType_i32, Encoded_GPR_##Src0(), Encoded_GPR_##Src1()); \ in TEST_F()
33 ASSERT_EQ(Value0, test.Src0()) << TestString; \ in TEST_F()
39 #define TestImpl(Dst, Src0, Src1) \ in TEST_F() argument
41 TestJ(o, Near, Dst, Src0, 0x80000000ul, Src1, 0x1ul); \ in TEST_F()
42 TestJ(o, Far, Dst, Src0, 0x80000000ul, Src1, 0x1ul); \ in TEST_F()
43 TestJ(no, Near, Dst, Src0, 0x1ul, Src1, 0x1ul); \ in TEST_F()
44 TestJ(no, Far, Dst, Src0, 0x1ul, Src1, 0x1ul); \ in TEST_F()
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DDataMov.cpp422 #define TestRegReg(C, Dest, IsTrue, Src0, Value0, Src1, Value1) \ in TEST_F() argument
425 "(" #C ", " #Dest ", " #IsTrue ", " #Src0 ", " #Value0 ", " #Src1 \ in TEST_F()
427 __ mov(IceType_i32, Encoded_GPR_##Src0(), Immediate(Value0)); \ in TEST_F()
430 __ cmp(IceType_i32, Encoded_GPR_##Src0(), Encoded_GPR_##Src1()); \ in TEST_F()
441 #define TestRegAddr(C, Dest, IsTrue, Src0, Value0, Value1) \ in TEST_F() argument
444 "(" #C ", " #Dest ", " #IsTrue ", " #Src0 ", " #Value0 \ in TEST_F()
448 __ mov(IceType_i32, Encoded_GPR_##Src0(), Immediate(Value0)); \ in TEST_F()
450 __ cmp(IceType_i32, Encoded_GPR_##Src0(), dwordAddress(T0)); \ in TEST_F()
462 #define TestValue(C, Dest, IsTrue, Src0, Value0, Src1, Value1) \ in TEST_F() argument
464 TestRegReg(C, Dest, IsTrue, Src0, Value0, Src1, Value1); \ in TEST_F()
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DGPRArith.cpp33 #define TestSetCC(C, Dest, IsTrue, Src0, Value0, Src1, Value1) \ in TEST_F() argument
36 "(" #C ", " #Dest ", " #IsTrue ", " #Src0 ", " #Value0 ", " #Src1 \ in TEST_F()
40 __ mov(IceType_i32, Encoded_GPR_##Src0(), Immediate(Value0)); \ in TEST_F()
42 __ cmp(IceType_i32, Encoded_GPR_##Src0(), Encoded_GPR_##Src1()); \ in TEST_F()
57 #define TestImpl(Dest, Src0, Src1) \ in TEST_F() argument
59 TestSetCC(o, Dest, 1u, Src0, 0x80000000u, Src1, 0x1u); \ in TEST_F()
60 TestSetCC(o, Dest, 0u, Src0, 0x1u, Src1, 0x10000000u); \ in TEST_F()
61 TestSetCC(no, Dest, 1u, Src0, 0x1u, Src1, 0x10000000u); \ in TEST_F()
62 TestSetCC(no, Dest, 0u, Src0, 0x80000000u, Src1, 0x1u); \ in TEST_F()
63 TestSetCC(b, Dest, 1u, Src0, 0x1, Src1, 0x80000000u); \ in TEST_F()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DMachineIRBuilder.h1226 MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1229 return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1243 MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1246 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1259 MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1262 return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1265 MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0,
1268 return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1271 MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0,
1274 return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
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DConstantFoldingMIRBuilder.h50 const SrcOp &Src0 = SrcOps[0]; variable
53 ConstantFoldBinOp(Opc, Src0.getReg(), Src1.getReg(), *getMRI()))
61 const SrcOp &Src0 = SrcOps[0]; variable
64 ConstantFoldExtOp(Opc, Src0.getReg(), Src1.getImm(), *getMRI()))
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600ExpandSpecialInstrs.cpp158 Register Src0 = in runOnMachineFunction() local
164 (void) Src0; in runOnMachineFunction()
166 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 && in runOnMachineFunction()
168 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1)); in runOnMachineFunction()
210 Register Src0 = in runOnMachineFunction() local
223 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
229 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
230 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
264 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1); in runOnMachineFunction()
DSIShrinkInstructions.cpp78 MachineOperand &Src0 = MI.getOperand(Src0Idx); in foldImmediates() local
79 if (Src0.isReg()) { in foldImmediates()
80 Register Reg = Src0.getReg(); in foldImmediates()
91 Src0.setSubReg(0); in foldImmediates()
92 Src0.ChangeToImmediate(MovSrc.getImm()); in foldImmediates()
95 Src0.setSubReg(0); in foldImmediates()
96 Src0.ChangeToFrameIndex(MovSrc.getIndex()); in foldImmediates()
99 Src0.ChangeToGA(MovSrc.getGlobal(), MovSrc.getOffset(), in foldImmediates()
321 MachineOperand *Src0 = &MI.getOperand(1); in shrinkScalarLogicOp() local
323 MachineOperand *SrcReg = Src0; in shrinkScalarLogicOp()
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DSIFoldOperands.cpp1004 MachineOperand *Src0 = getImmOrMaterializedImm(MRI, MI->getOperand(Src0Idx)); in tryConstantFoldOp() local
1007 if (!Src0->isImm() && !Src1->isImm()) in tryConstantFoldOp()
1011 if (Src0->isImm() && Src0->getImm() == 0) { in tryConstantFoldOp()
1026 if (Src0->isImm() && Src1->isImm()) { in tryConstantFoldOp()
1028 if (!evalBinaryInstruction(Opc, NewImm, Src0->getImm(), Src1->getImm())) in tryConstantFoldOp()
1045 if (Src0->isImm() && !Src1->isImm()) { in tryConstantFoldOp()
1046 std::swap(Src0, Src1); in tryConstantFoldOp()
1108 const MachineOperand *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0); in tryFoldInst() local
1112 if (Src1->isIdenticalTo(*Src0) && in tryFoldInst()
1117 TII->get(Src0->isReg() ? (unsigned)AMDGPU::COPY : getMovOpc(false)); in tryFoldInst()
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DSIInstrInfo.cpp1631 MachineOperand &Src0, in swapSourceModifiers() argument
1690 MachineOperand &Src0 = MI.getOperand(Src0Idx); in commuteInstructionImpl() local
1694 if (Src0.isReg() && Src1.isReg()) { in commuteInstructionImpl()
1695 if (isOperandLegal(MI, Src1Idx, &Src0)) { in commuteInstructionImpl()
1701 } else if (Src0.isReg() && !Src1.isReg()) { in commuteInstructionImpl()
1704 CommutedMI = swapRegAndNonRegOperand(MI, Src0, Src1); in commuteInstructionImpl()
1705 } else if (!Src0.isReg() && Src1.isReg()) { in commuteInstructionImpl()
1706 if (isOperandLegal(MI, Src1Idx, &Src0)) in commuteInstructionImpl()
1707 CommutedMI = swapRegAndNonRegOperand(MI, Src1, Src0); in commuteInstructionImpl()
1714 swapSourceModifiers(MI, Src0, AMDGPU::OpName::src0_modifiers, in commuteInstructionImpl()
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DSIPeepholeSDWA.cpp563 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
564 auto Imm = foldToImm(*Src0); in matchSDWAOperand()
604 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
605 auto Imm = foldToImm(*Src0); in matchSDWAOperand()
673 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
676 if (Register::isPhysicalRegister(Src0->getReg()) || in matchSDWAOperand()
681 Src0, Dst, SrcSel, false, false, Opcode != AMDGPU::V_BFE_U32); in matchSDWAOperand()
690 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
693 auto Imm = foldToImm(*Src0); in matchSDWAOperand()
697 ValSrc = Src0; in matchSDWAOperand()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp298 unsigned Src0 = 0, SubReg0; in transformInstruction() local
309 Src0 = MOSrc0->getReg(); in transformInstruction()
341 if (!Src0) { in transformInstruction()
343 Src0 = MRI->createVirtualRegister(&AArch64::FPR64RegClass); in transformInstruction()
344 insertCopy(TII, MI, Src0, OrigSrc0, KillSrc0); in transformInstruction()
363 .addReg(Src0, getKillRegState(KillSrc0), SubReg0) in transformInstruction()
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/unittest/AssemblerX8632/
DGPRArith.cpp48 #define TestSetCC(C, Src0, Value0, Src1, Value1, Dest, IsTrue) \ in TEST_F() argument
52 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Src0, Immediate(Value0)); \ in TEST_F()
54 __ cmp(IceType_i32, GPRRegister::Encoded_Reg_##Src0, \ in TEST_F()
66 << "(" #C ", " #Src0 ", " #Value0 ", " #Src1 ", " #Value1 ", " #Dest \ in TEST_F()
69 << "(" #C ", " #Src0 ", " #Value0 ", " #Src1 ", " #Value1 ", " #Dest \ in TEST_F()
678 #define TestImplRegReg(Inst0, Inst1, Dst0, Dst1, Value0, Src0, Src1, Value1, \ in TEST_F() argument
684 "(" #Inst0 ", " #Inst1 ", " #Dst0 ", " #Dst1 ", " #Value0 ", " #Src0 \ in TEST_F()
690 __ mov(IceType_i##Size, GPRRegister::Encoded_Reg_##Src0, \ in TEST_F()
695 GPRRegister::Encoded_Reg_##Src0); \ in TEST_F()
773 #define TestImplAddrReg(Inst0, Inst1, Value0, Src0, Src1, Value1, Op, Size) \ in TEST_F() argument
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