Searched refs:SrcHi (Results 1 – 9 of 9) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.cpp | 55 unsigned DestLo, DestHi, SrcLo, SrcHi; in copyPhysReg() local
58 TRI.splitReg(SrcReg, SrcLo, SrcHi); in copyPhysReg()
64 .addReg(SrcHi, getKillRegState(KillSrc)); in copyPhysReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 725 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); in expandPseudoMTLoHi() local
740 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill())); in expandPseudoMTLoHi()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1784 Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi); in expandStoreVec2() local
1810 if (LPR.contains(SrcHi)) { in expandStoreVec2()
1816 .addReg(SrcHi, getKillRegState(IsKill)) in expandStoreVec2()
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| D | HexagonInstrInfo.cpp | 1303 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo() local
1307 .addReg(SrcHi) in expandPostRAPseudo()
1315 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo() local
1319 .addReg(SrcHi) in expandPostRAPseudo()
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| /third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringX8632.cpp | 6284 Operand *SrcHi = hiOperand(Src); in lowerMove() local
6290 _mov(T_Hi, SrcHi); in lowerMove()
6774 Operand *SrcHi = legalize(hiOperand(Src), Legal_Reg | Legal_Imm); in lowerRMW() local
6783 _adc_rmw(AddrHi, SrcHi); in lowerRMW()
6787 _sbb_rmw(AddrHi, SrcHi); in lowerRMW()
6791 _and_rmw(AddrHi, SrcHi); in lowerRMW()
6795 _or_rmw(AddrHi, SrcHi); in lowerRMW()
6799 _xor_rmw(AddrHi, SrcHi); in lowerRMW()
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| D | IceInstARM32.cpp | 1853 auto *SrcHi = llvm::cast<Variable>(getSrc(1)); in emitSingleDestMultiSource() local
1855 assert(SrcHi->hasReg()); in emitSingleDestMultiSource()
1867 SrcHi->emit(Func); in emitSingleDestMultiSource()
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| D | IceTargetLoweringARM32.h | 313 void div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi);
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| D | IceTargetLoweringARM32.cpp | 2099 void TargetARM32::div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi) { in div0Check() argument
2100 if (isGuaranteedNonzeroInt(SrcLo) || isGuaranteedNonzeroInt(SrcHi)) in div0Check()
2120 _orrs(T, SrcLoReg, legalize(SrcHi, Legal_Reg | Legal_Flex)); in div0Check()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 6097 SDValue SrcHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, SrcVec, in LowerINTRINSIC_WO_CHAIN() local
6099 return DAG.getSetCC(SL, MVT::i1, SrcHi, Aperture, ISD::SETEQ); in LowerINTRINSIC_WO_CHAIN()
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