| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.cpp | 38 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in copyPhysReg() local
40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
49 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr in copyPhysReg()
52 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr in copyPhysReg()
55 Op = (SrcRC == &NVPTX::Float16RegsRegClass ? NVPTX::FMOV16rr in copyPhysReg()
60 Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr in copyPhysReg()
63 Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr in copyPhysReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 174 const TargetRegisterClass *SrcRC = Register::isVirtualRegister(SrcReg) in getCopyRegClasses() local
185 return std::make_pair(SrcRC, DstRC); in getCopyRegClasses()
188 static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC, in isVGPRToSGPRCopy() argument
191 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) && in isVGPRToSGPRCopy()
192 TRI.hasVectorRegisters(SrcRC); in isVGPRToSGPRCopy()
195 static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC, in isSGPRToVGPRCopy() argument
198 return DstRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(SrcRC) && in isSGPRToVGPRCopy()
261 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local
262 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); in foldVGPRCopyIntoRegSequence()
264 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) in foldVGPRCopyIntoRegSequence()
[all …]
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| D | AMDGPUInstructionSelector.cpp | 115 const TargetRegisterClass *SrcRC in selectCOPY() local
118 Register MaskedReg = MRI->createVirtualRegister(SrcRC); in selectCOPY()
124 unsigned AndOpc = TRI.isSGPRClass(SrcRC) ? in selectCOPY()
134 MRI->setRegClass(SrcReg, SrcRC); in selectCOPY()
151 const TargetRegisterClass *SrcRC = in selectCOPY() local
153 if (SrcRC && !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI)) in selectCOPY()
463 const TargetRegisterClass *SrcRC = in selectG_EXTRACT() local
465 if (!SrcRC) in selectG_EXTRACT()
468 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8); in selectG_EXTRACT()
511 const TargetRegisterClass *SrcRC in selectG_MERGE_VALUES() local
[all …]
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| D | SIRegisterInfo.h | 183 const TargetRegisterClass *SrcRC,
237 const TargetRegisterClass *SrcRC,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstructionSelector.cpp | 111 const TargetRegisterClass *SrcRC) const;
247 const TargetRegisterClass *SrcRC = in selectCopy() local
251 if (SrcRC != DstRC) { in selectCopy()
259 .addImm(getSubRegIndex(SrcRC)); in selectCopy()
285 const TargetRegisterClass *SrcRC = getRegClassFromGRPhysReg(SrcReg); in selectCopy() local
287 if (DstRC != SrcRC) { in selectCopy()
684 const TargetRegisterClass *SrcRC) { in canTurnIntoCOPY() argument
687 (SrcRC == &X86::VR128RegClass || SrcRC == &X86::VR128XRegClass); in canTurnIntoCOPY()
693 const TargetRegisterClass *SrcRC) const { in selectTurnIntoCOPY()
695 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) || in selectTurnIntoCOPY()
[all …]
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| D | X86DomainReassignment.cpp | 66 static const TargetRegisterClass *getDstRC(const TargetRegisterClass *SrcRC, in getDstRC() argument
69 if (X86::GR8RegClass.hasSubClassEq(SrcRC)) in getDstRC()
71 if (X86::GR16RegClass.hasSubClassEq(SrcRC)) in getDstRC()
73 if (X86::GR32RegClass.hasSubClassEq(SrcRC)) in getDstRC()
75 if (X86::GR64RegClass.hasSubClassEq(SrcRC)) in getDstRC()
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| D | X86RegisterInfo.h | 79 const TargetRegisterClass *SrcRC,
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| D | X86InstrMMX.td | 126 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
129 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
130 [(set DstRC:$dst, (Int SrcRC:$src))], d>,
137 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
141 (ins DstRC:$src1, SrcRC:$src2), asm,
142 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>,
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| D | X86RegisterInfo.cpp | 221 const TargetRegisterClass *SrcRC, in shouldRewriteCopySrc() argument
227 SrcRC->hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit) in shouldRewriteCopySrc()
231 SrcRC, SrcSubReg); in shouldRewriteCopySrc()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 345 const TargetRegisterClass *SrcRC, in shareSameRegisterFile() argument
348 if (DefRC == SrcRC) in shareSameRegisterFile()
354 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, in shareSameRegisterFile()
362 std::swap(DefRC, SrcRC); in shareSameRegisterFile()
367 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; in shareSameRegisterFile()
370 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
375 const TargetRegisterClass *SrcRC, in shouldRewriteCopySrc() argument
378 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg); in shouldRewriteCopySrc()
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| D | DetectDeadLanes.cpp | 158 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in isCrossCopy() local
159 if (DstRC == SrcRC) in isCrossCopy()
184 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, in isCrossCopy()
187 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx); in isCrossCopy()
189 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); in isCrossCopy()
190 return !TRI.getCommonSubClass(SrcRC, DstRC); in isCrossCopy()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXCopy.cpp | 99 const TargetRegisterClass *SrcRC = &PPC::VSLRCRegClass; in processBlock() local
105 Register NewVReg = MRI.createVirtualRegister(SrcRC); in processBlock()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MicroMips32r6InstrInfo.td | 658 RegisterOperand SrcRC, InstrItinClass Itin> {
659 dag InOperandList = (ins SrcRC:$rt, uimm3:$sel);
668 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
671 dag InOperandList = (ins SrcRC:$rt);
674 list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
680 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
682 dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
694 RegisterOperand SrcRC, InstrItinClass Itin> {
695 dag InOperandList = (ins SrcRC:$rt);
716 RegisterOperand SrcRC, InstrItinClass Itin> {
[all …]
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| D | MipsInstrFPU.td | 125 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
127 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
128 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
132 class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
135 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft),
137 [(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>,
159 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
161 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
162 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT {
166 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | InstructionSelect.cpp | 174 auto SrcRC = MRI.getRegClass(SrcReg); in runOnMachineFunction() local
176 if (SrcRC == DstRC) { in runOnMachineFunction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.h | 59 const TargetRegisterClass *SrcRC,
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| D | AVRRegisterInfo.cpp | 277 const TargetRegisterClass *SrcRC, in shouldCoalesce() argument
287 return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg, NewRC, LIS); in shouldCoalesce()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.h | 63 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
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| D | HexagonRegisterInfo.cpp | 241 const TargetRegisterClass *SrcRC, unsigned SubReg, in shouldCoalesce() argument
252 bool SmallSrc = SrcRC->getID() == Hexagon::HvxVRRegClass.getID(); in shouldCoalesce()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.h | 88 const TargetRegisterClass *SrcRC,
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| D | SystemZRegisterInfo.cpp | 341 const TargetRegisterClass *SrcRC, in shouldCoalesce() argument
351 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64))) in shouldCoalesce()
358 unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0); in shouldCoalesce()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.h | 207 const TargetRegisterClass *SrcRC,
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| D | ARMBaseRegisterInfo.cpp | 837 const TargetRegisterClass *SrcRC, in shouldCoalesce() argument
852 getRegSizeInBits(*SrcRC) < 256) in shouldCoalesce()
858 MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC); in shouldCoalesce()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGFast.cpp | 382 const TargetRegisterClass *SrcRC, in InsertCopiesAndMoveSuccs() argument
385 CopyFromSU->CopySrcRC = SrcRC; in InsertCopiesAndMoveSuccs()
390 CopyToSU->CopyDstRC = SrcRC; in InsertCopiesAndMoveSuccs()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 536 const TargetRegisterClass *SrcRC,
947 const TargetRegisterClass *SrcRC, in shouldCoalesce() argument
|