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Searched refs:SrcVT (Results 1 – 25 of 41) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp172 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
828 MVT SrcVT = SrcEVT.getSimpleVT(); in PPCEmitCmp() local
830 if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits()) in PPCEmitCmp()
844 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 || in PPCEmitCmp()
845 SrcVT == MVT::i8 || SrcVT == MVT::i1) { in PPCEmitCmp()
870 switch (SrcVT.SimpleTy) { in PPCEmitCmp()
935 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
941 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) in PPCEmitCmp()
960 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in SelectFPExt() local
963 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in SelectFPExt()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsFastISel.cpp187 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
188 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
191 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
193 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
194 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
196 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1000 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in selectFPExt() local
1003 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in selectFPExt()
1079 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in selectFPTrunc() local
1082 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in selectFPTrunc()
[all …]
DMipsMSAInstrInfo.td3592 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3594 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3595 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3649 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3652 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3653 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3657 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3660 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3661 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3665 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp196 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
233 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
264 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
268 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
272 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
1183 MVT SrcVT = RetVT; in emitAddSub() local
1210 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1308 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
2881 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true); in selectFPToInt() local
2882 if (SrcVT == MVT::f128 || SrcVT == MVT::f16) in selectFPToInt()
[all …]
DAArch64TargetTransformInfo.cpp427 auto SrcVT = TLI->getValueType(DL, Src); in getExtractWithExtendCost() local
437 if (DstVT.getSizeInBits() < SrcVT.getSizeInBits()) in getExtractWithExtendCost()
452 if (DstVT.getSizeInBits() != 64u || SrcVT.getSizeInBits() == 32u) in getExtractWithExtendCost()
DAArch64ISelLowering.cpp5088 EVT SrcVT = In2.getValueType(); in LowerFCOPYSIGN() local
5090 if (SrcVT.bitsLT(VT)) in LowerFCOPYSIGN()
5092 else if (SrcVT.bitsGT(VT)) in LowerFCOPYSIGN()
6622 EVT SrcVT = Src.ShuffleVec.getValueType(); in ReconstructShuffle() local
6624 if (SrcVT.getSizeInBits() == VT.getSizeInBits()) in ReconstructShuffle()
6629 EVT EltVT = SrcVT.getVectorElementType(); in ReconstructShuffle()
6633 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) { in ReconstructShuffle()
6634 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits()); in ReconstructShuffle()
6643 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits()); in ReconstructShuffle()
8379 EVT SrcVT = LHS.getValueType(); in EmitVectorComparison() local
[all …]
DAArch64ISelDAGToDAG.cpp490 EVT SrcVT; in getExtendTypeForNode() local
492 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT(); in getExtendTypeForNode()
494 SrcVT = N.getOperand(0).getValueType(); in getExtendTypeForNode()
496 if (!IsLoadStore && SrcVT == MVT::i8) in getExtendTypeForNode()
498 else if (!IsLoadStore && SrcVT == MVT::i16) in getExtendTypeForNode()
500 else if (SrcVT == MVT::i32) in getExtendTypeForNode()
502 assert(SrcVT != MVT::i64 && "extend from 64-bits?"); in getExtendTypeForNode()
507 EVT SrcVT = N.getOperand(0).getValueType(); in getExtendTypeForNode() local
508 if (!IsLoadStore && SrcVT == MVT::i8) in getExtendTypeForNode()
510 else if (!IsLoadStore && SrcVT == MVT::i16) in getExtendTypeForNode()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp708 EVT SrcVT = LD->getMemoryVT(); in ExpandLoad() local
709 EVT SrcEltVT = SrcVT.getScalarType(); in ExpandLoad()
710 unsigned NumElem = SrcVT.getVectorNumElements(); in ExpandLoad()
714 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) { in ExpandLoad()
740 unsigned RemainingBytes = SrcVT.getStoreSize(); in ExpandLoad()
1079 EVT SrcVT = Src.getValueType(); in ExpandANY_EXTEND_VECTOR_INREG() local
1080 int NumSrcElements = SrcVT.getVectorNumElements(); in ExpandANY_EXTEND_VECTOR_INREG()
1084 if (SrcVT.bitsLE(VT)) { in ExpandANY_EXTEND_VECTOR_INREG()
1085 assert((VT.getSizeInBits() % SrcVT.getScalarSizeInBits()) == 0 && in ExpandANY_EXTEND_VECTOR_INREG()
1087 NumSrcElements = VT.getSizeInBits() / SrcVT.getScalarSizeInBits(); in ExpandANY_EXTEND_VECTOR_INREG()
[all …]
DTargetLowering.cpp630 EVT SrcVT = Src.getValueType(); in SimplifyMultipleUseDemandedBits() local
632 unsigned NumSrcEltBits = SrcVT.getScalarSizeInBits(); in SimplifyMultipleUseDemandedBits()
641 if (SrcVT.isVector() && (NumDstEltBits % NumSrcEltBits) == 0 && in SimplifyMultipleUseDemandedBits()
644 unsigned NumSrcElts = SrcVT.getVectorNumElements(); in SimplifyMultipleUseDemandedBits()
667 unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; in SimplifyMultipleUseDemandedBits()
1680 EVT SrcVT = Src.getValueType(); in SimplifyDemandedBits() local
1681 unsigned InBits = SrcVT.getScalarSizeInBits(); in SimplifyDemandedBits()
1682 unsigned InElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; in SimplifyDemandedBits()
1690 VT.getSizeInBits() == SrcVT.getSizeInBits() && in SimplifyDemandedBits()
1713 EVT SrcVT = Src.getValueType(); in SimplifyDemandedBits() local
[all …]
DFastISel.cpp1492 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); in selectCast() local
1495 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other || in selectCast()
1505 if (!TLI.isTypeLegal(SrcVT)) in selectCast()
1515 unsigned ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), in selectCast()
1542 MVT SrcVT = SrcEVT.getSimpleVT(); in selectBitCast() local
1551 if (SrcVT == DstVT) { in selectBitCast()
1552 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT); in selectBitCast()
1564 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill); in selectBitCast()
1898 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); in selectOperator() local
1900 if (DstVT.bitsGT(SrcVT)) in selectOperator()
[all …]
DLegalizeDAG.cpp722 EVT SrcVT = LD->getMemoryVT(); in LegalizeLoadOps() local
723 unsigned SrcWidth = SrcVT.getSizeInBits(); in LegalizeLoadOps()
728 if (SrcWidth != SrcVT.getStoreSizeInBits() && in LegalizeLoadOps()
736 (SrcVT != MVT::i1 || in LegalizeLoadOps()
741 unsigned NewWidth = SrcVT.getStoreSizeInBits(); in LegalizeLoadOps()
761 Result, DAG.getValueType(SrcVT)); in LegalizeLoadOps()
766 DAG.getValueType(SrcVT)); in LegalizeLoadOps()
772 assert(!SrcVT.isVector() && "Unsupported extload!"); in LegalizeLoadOps()
850 SrcVT.getSimpleVT())) { in LegalizeLoadOps()
878 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) { in LegalizeLoadOps()
[all …]
DLegalizeFloatTypes.cpp1560 EVT SrcVT = Src.getValueType(); in ExpandFloatRes_XINT_TO_FP() local
1567 if (SrcVT.bitsLE(MVT::i32)) { in ExpandFloatRes_XINT_TO_FP()
1576 if (SrcVT.bitsLE(MVT::i64)) { in ExpandFloatRes_XINT_TO_FP()
1580 } else if (SrcVT.bitsLE(MVT::i128)) { in ExpandFloatRes_XINT_TO_FP()
1597 SrcVT = Src.getValueType(); in ExpandFloatRes_XINT_TO_FP()
1605 switch (SrcVT.getSimpleVT().SimpleTy) { in ExpandFloatRes_XINT_TO_FP()
1624 Lo = DAG.getSelectCC(dl, Src, DAG.getConstant(0, dl, SrcVT), in ExpandFloatRes_XINT_TO_FP()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMFastISel.cpp205 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1355 MVT SrcVT = SrcEVT.getSimpleVT(); in ARMEmitCmp() local
1371 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 || in ARMEmitCmp()
1372 SrcVT == MVT::i1) { in ARMEmitCmp()
1386 if (SrcVT == MVT::f32 || SrcVT == MVT::f64) in ARMEmitCmp()
1394 switch (SrcVT.SimpleTy) { in ARMEmitCmp()
1436 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt); in ARMEmitCmp()
1439 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); in ARMEmitCmp()
1550 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIToFP() local
1551 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) in SelectIToFP()
[all …]
DARMISelLowering.h355 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
522 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86FastISel.cpp97 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
706 unsigned Src, EVT SrcVT, in X86FastEmitExtend() argument
708 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, in X86FastEmitExtend()
1222 EVT SrcVT = TLI.getValueType(DL, RV->getType()); in X86SelectRet() local
1225 if (SrcVT != DstVT) { in X86SelectRet()
1226 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16) in X86SelectRet()
1234 if (SrcVT == MVT::i1) { in X86SelectRet()
1238 SrcVT = MVT::i8; in X86SelectRet()
1242 SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, in X86SelectRet()
1530 MVT SrcVT = TLI.getSimpleValueType(DL, I->getOperand(0)->getType()); in X86SelectZExt() local
[all …]
DX86SelectionDAGInfo.cpp281 EVT SrcVT = Src.getValueType(); in emitConstantSizeRepmov() local
285 DAG.getNode(ISD::ADD, dl, SrcVT, Src, DAG.getConstant(Offset, dl, SrcVT)), in emitConstantSizeRepmov()
DX86ISelLowering.cpp5116 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
5124 return Index == 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits()*2) && in isExtractSubvectorCheap()
6410 EVT SrcVT = Op.getOperand(0).getValueType(); in getTargetConstantBitsFromNode() local
6411 unsigned NumSrcElts = SrcVT.getVectorNumElements(); in getTargetConstantBitsFromNode()
7326 EVT SrcVT = SrcVec.getValueType(); in getFauxShuffleMask() local
7327 unsigned NumSrcElts = SrcVT.getVectorNumElements(); in getFauxShuffleMask()
7328 unsigned NumZeros = (NumBitsPerElt / SrcVT.getScalarSizeInBits()) - 1; in getFauxShuffleMask()
7449 MVT SrcVT = Src.getSimpleValueType(); in getFauxShuffleMask() local
7450 if (!SrcVT.isVector()) in getFauxShuffleMask()
7453 if (NumSizeInBits != SrcVT.getSizeInBits()) { in getFauxShuffleMask()
[all …]
DX86ISelLowering.h819 ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const override;
1157 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
1230 std::pair<SDValue, SDValue> BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTypePromotion.cpp975 EVT SrcVT = TLI->getValueType(DL, I->getType()); in runOnFunction() local
976 if (SrcVT.isSimple() && TLI->isTypeLegal(SrcVT.getSimpleVT())) in runOnFunction()
979 if (TLI->getTypeAction(ICmp->getContext(), SrcVT) != in runOnFunction()
983 EVT PromotedVT = TLI->getTypeToTransformTo(ICmp->getContext(), SrcVT); in runOnFunction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.td279 class isFloatType<ValueType SrcVT> {
281 !if(!eq(SrcVT.Value, f16.Value), 1,
282 !if(!eq(SrcVT.Value, f32.Value), 1,
283 !if(!eq(SrcVT.Value, f64.Value), 1,
284 !if(!eq(SrcVT.Value, v2f16.Value), 1,
285 !if(!eq(SrcVT.Value, v4f16.Value), 1,
286 !if(!eq(SrcVT.Value, v2f32.Value), 1,
287 !if(!eq(SrcVT.Value, v2f64.Value), 1,
291 class isIntType<ValueType SrcVT> {
293 !if(!eq(SrcVT.Value, i16.Value), 1,
[all …]
DAMDGPUISelLowering.cpp820 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const { in isNarrowingProfitable() argument
827 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32; in isNarrowingProfitable()
2509 EVT SrcVT = Src.getValueType(); in LowerUINT_TO_FP() local
2511 if (SrcVT == MVT::i16) { in LowerUINT_TO_FP()
2521 assert(SrcVT == MVT::i64 && "operation should be legal"); in LowerUINT_TO_FP()
2546 EVT SrcVT = Src.getValueType(); in LowerSINT_TO_FP() local
2548 if (SrcVT == MVT::i16) { in LowerSINT_TO_FP()
2558 assert(SrcVT == MVT::i64 && "operation should be legal"); in LowerSINT_TO_FP()
2715 EVT SrcVT = Src.getValueType(); in LowerFP_TO_SINT() local
2716 if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) { in LowerFP_TO_SINT()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVISelLowering.h74 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
76 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
DRISCVISelLowering.cpp312 bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const { in isTruncateFree() argument
313 if (Subtarget.is64Bit() || SrcVT.isVector() || DstVT.isVector() || in isTruncateFree()
314 !SrcVT.isInteger() || !DstVT.isInteger()) in isTruncateFree()
316 unsigned SrcBits = SrcVT.getSizeInBits(); in isTruncateFree()
335 bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const { in isSExtCheaperThanZExt() argument
336 return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64; in isSExtCheaperThanZExt()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/
DScalarizer.cpp684 VectorType *SrcVT = dyn_cast<VectorType>(BCI.getSrcTy()); in visitBitCastInst() local
685 if (!DstVT || !SrcVT) in visitBitCastInst()
689 unsigned SrcNumElems = SrcVT->getNumElements(); in visitBitCastInst()
721 Type *MidTy = VectorType::get(SrcVT->getElementType(), FanIn); in visitBitCastInst()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DTargetLowering.h2476 virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const { in isFPExtFree() argument
2477 assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() && in isFPExtFree()
2486 EVT DestVT, EVT SrcVT) const { in isFPExtFoldable() argument
2487 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() && in isFPExtFoldable()
2489 return isFPExtFree(DestVT, SrcVT); in isFPExtFoldable()
2557 virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, in isExtractSubvectorCheap() argument
3359 ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const { in isDesirableToCombineBuildVectorToShuffleTruncate() argument

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