| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SILoadStoreOptimizer.cpp | 982 const TargetRegisterClass *SuperRC = in mergeRead2Pair() local
984 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeRead2Pair()
1124 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeImagePair() local
1126 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeImagePair()
1177 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeSBufferLoadImmPair() local
1179 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeSBufferLoadImmPair()
1228 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeBufferLoadPair() local
1231 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeBufferLoadPair()
1290 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeTBufferLoadPair() local
1293 Register DestReg = MRI->createVirtualRegister(SuperRC); in mergeTBufferLoadPair()
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| D | SIInstrInfo.h | 72 const TargetRegisterClass *SuperRC,
78 const TargetRegisterClass *SuperRC,
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| D | SIInstrInfo.cpp | 3864 const TargetRegisterClass *SuperRC, in buildExtractSubReg() argument
3882 Register NewSuperReg = MRI.createVirtualRegister(SuperRC); in buildExtractSubReg()
3897 const TargetRegisterClass *SuperRC, in buildExtractSubRegOrImm() argument
3909 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC, in buildExtractSubRegOrImm()
3936 const TargetRegisterClass *SuperRC = RI.getLargestLegalSuperClass(RC, *MF); in isLegalRegOperand() local
3937 if (!SuperRC) in isLegalRegOperand()
3940 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg()); in isLegalRegOperand()
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| D | AMDGPUISelDAGToDAG.cpp | 596 const TargetRegisterClass *SuperRC = in getOperandRegClass() local
601 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC, in getOperandRegClass()
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| D | SIISelLowering.cpp | 3324 const TargetRegisterClass *SuperRC, in computeIndirectRegAndOffset() argument
3327 int NumElts = TRI.getRegSizeInBits(*SuperRC) / 32; in computeIndirectRegAndOffset()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 629 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
632 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
640 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size())); in FindSuitableFreeRegisters()
642 unsigned OrigR = RenameOrder[SuperRC]; in FindSuitableFreeRegisters()
736 RenameOrder.erase(SuperRC); in FindSuitableFreeRegisters()
737 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R)); in FindSuitableFreeRegisters()
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| D | MachineCopyPropagation.cpp | 435 const TargetRegisterClass *SuperRC = UseDstRC; in isForwardableRegClassCopy() local
437 SuperRC; SuperRC = *SuperRCI++) in isForwardableRegClassCopy()
438 if (SuperRC->contains(CopySrcReg)) in isForwardableRegClassCopy()
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| D | RegAllocGreedy.cpp | 2065 const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC, in getNumAllocatableRegsForConstraints() argument
2068 assert(SuperRC && "Invalid register class"); in getNumAllocatableRegsForConstraints()
2071 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI, in getNumAllocatableRegsForConstraints()
2105 const TargetRegisterClass *SuperRC = in tryInstructionSplit() local
2107 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC); in tryInstructionSplit()
2116 getNumAllocatableRegsForConstraints(MI, VirtReg.reg, SuperRC, TII, in tryInstructionSplit()
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| D | TargetLoweringBase.cpp | 1128 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); in findRepresentativeClass() local
1130 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC)) in findRepresentativeClass()
1132 if (!isLegalRC(*TRI, *SuperRC)) in findRepresentativeClass()
1134 BestRC = SuperRC; in findRepresentativeClass()
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| D | MachineVerifier.cpp | 1790 const TargetRegisterClass *SuperRC = in visitMachineOperand() local
1792 if (!SuperRC) { in visitMachineOperand()
1796 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonCopyToCombine.cpp | 588 const TargetRegisterClass *SuperRC = nullptr; in combine() local
590 SuperRC = &Hexagon::DoubleRegsRegClass; in combine()
594 SuperRC = &Hexagon::HvxWRRegClass; in combine()
600 unsigned DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC); in combine()
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| D | HexagonRegisterInfo.cpp | 331 if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses()) in getHexagonSubRegIndex() local
332 return getHexagonSubRegIndex(*SuperRC, GenIdx); in getHexagonSubRegIndex()
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