| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIAddIMGInit.cpp | 79 MachineOperand *TFE = TII->getNamedOperand(MI, AMDGPU::OpName::tfe); in runOnMachineFunction() local
85 assert( (TFE && LWE) && "Expected tfe and lwe operands in instruction"); in runOnMachineFunction()
87 unsigned TFEVal = TFE->getImm(); in runOnMachineFunction()
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| D | MIMGInstructions.td | 229 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
241 SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe),
254 SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe),
322 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
334 GLC:$glc, SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe),
348 SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe),
411 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da);
439 GLC:$glc, SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe);
455 SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe));
513 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
[all …]
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| D | AMDGPUISelDAGToDAG.cpp | 211 SDValue &TFE, SDValue &DLC, SDValue &SWZ) const;
214 SDValue &SLC, SDValue &TFE, SDValue &DLC,
228 SDValue &TFE, SDValue &DLC, SDValue &SWZ) const;
1343 SDValue &TFE, SDValue &DLC, in SelectMUBUF() argument
1355 TFE = CurDAG->getTargetConstant(0, DL, MVT::i1); in SelectMUBUF()
1436 SDValue &SLC, SDValue &TFE, in SelectMUBUFAddr64() argument
1445 GLC, SLC, TFE, DLC, SWZ)) in SelectMUBUFAddr64()
1467 SDValue GLC, TFE, DLC, SWZ; in SelectMUBUFAddr64() local
1469 return SelectMUBUFAddr64(Addr, SRsrc, VAddr, SOffset, Offset, GLC, SLC, TFE, DLC, SWZ); in SelectMUBUFAddr64()
1594 SDValue &TFE, SDValue &DLC, in SelectMUBUFOffset() argument
[all …]
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| D | BUFInstructions.td | 144 offset:$offset, FORMAT:$format, GLC:$glc, SLC:$slc, TFE:$tfe, DLC:$dlc, SWZ:$swz),
146 offset:$offset, FORMAT:$format, GLC:$glc, SLC:$slc, TFE:$tfe, DLC:$dlc, SWZ:$swz)
151 SLC:$slc, TFE:$tfe, DLC:$dlc, SWZ:$swz),
154 SLC:$slc, TFE:$tfe, DLC:$dlc, SWZ:$swz)
415 !if(isLds, (ins DLC:$dlc, SWZ:$swz), (ins TFE:$tfe, DLC:$dlc,SWZ:$swz))
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| D | SIInstrInfo.cpp | 3408 const MachineOperand *TFE = getNamedOperand(MI, AMDGPU::OpName::tfe); in verifyInstruction() local
3417 if ((LWE && LWE->getImm()) || (TFE && TFE->getImm())) in verifyInstruction()
4786 if (const MachineOperand *TFE = in legalizeOperands() local
4788 MIB.addImm(TFE->getImm()); in legalizeOperands()
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| D | SIInstrInfo.td | 1065 def TFE : NamedOperandBit<"TFE", NamedMatchClass<"TFE">>;
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| D | FLATInstructions.td | 124 let Inst{55} = nv; // nv on GFX9+, TFE before.
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| D | SIISelLowering.cpp | 5316 static bool parseTexFail(SDValue TexFailCtrl, SelectionDAG &DAG, SDValue *TFE, in parseTexFail() argument
5326 *TFE = DAG.getTargetConstant((Value & 0x1) ? 1 : 0, DL, MVT::i32); in parseTexFail()
5528 SDValue TFE; in lowerImage() local
5532 if (!parseTexFail(TexFail, DAG, &TFE, &LWE, IsTexFail)) in lowerImage()
5608 Ops.push_back(TFE); // tfe in lowerImage()
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| /third_party/chromium/patch/ |
| D | 0001-cve.patch | 71129 zpNJx#QooS?`J8$|y(oS4x9S!3I}zn;TFE)v6c07!4BOUIOYP|y_->YnZ+1BbGxEMw
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