| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 2767 ISD = IsUnsigned ? ISD::UMIN : ISD::SMIN; in getMinMaxReductionCost()
2784 {ISD::UMIN, MVT::v2i64, 8}, in getMinMaxReductionCost()
2786 {ISD::UMIN, MVT::v4i32, 8}, in getMinMaxReductionCost()
2788 {ISD::UMIN, MVT::v8i16, 6}, in getMinMaxReductionCost()
2790 {ISD::UMIN, MVT::v16i8, 6}, in getMinMaxReductionCost()
2796 {ISD::UMIN, MVT::v2i64,10}, in getMinMaxReductionCost()
2798 {ISD::UMIN, MVT::v4i32, 2}, // The data reported by the IACA is "1.8" in getMinMaxReductionCost()
2800 {ISD::UMIN, MVT::v8i16, 2}, in getMinMaxReductionCost()
2802 {ISD::UMIN, MVT::v16i8, 3}, in getMinMaxReductionCost()
2807 {ISD::UMIN, MVT::v2i64, 8}, // The data reported by the IACA is "8.6" in getMinMaxReductionCost()
[all …]
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| D | X86ISelLowering.cpp | 906 setOperationAction(ISD::UMIN, VT, VT == MVT::v16i8 ? Legal : Custom); in X86TargetLowering()
1089 setOperationAction(ISD::UMIN, MVT::v8i16, Legal); in X86TargetLowering()
1090 setOperationAction(ISD::UMIN, MVT::v4i32, Legal); in X86TargetLowering()
1287 setOperationAction(ISD::UMIN, MVT::v4i64, Custom); in X86TargetLowering()
1303 setOperationAction(ISD::UMIN, VT, HasInt256 ? Legal : Custom); in X86TargetLowering()
1562 setOperationAction(ISD::UMIN, VT, Legal); in X86TargetLowering()
1674 setOperationAction(ISD::UMIN, VT, Legal); in X86TargetLowering()
1819 setOperationAction(ISD::UMIN, VT, Legal); in X86TargetLowering()
21592 TLI.isOperationLegal(ISD::UMIN, VT)) { in LowerVSETCC()
21614 case ISD::SETULE: Opc = ISD::UMIN; break; in LowerVSETCC()
[all …]
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| /third_party/ffmpeg/tests/ref/fate/ |
| D | filter-metadata-signalstats-yuv420p10 | 1 …ignalstats.YHIGH=940|tag:lavfi.signalstats.YMAX=940|tag:lavfi.signalstats.UMIN=512|tag:lavfi.signa…
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| D | filter-metadata-signalstats-yuv420p | 1 …ignalstats.YHIGH=235|tag:lavfi.signalstats.YMAX=235|tag:lavfi.signalstats.UMIN=128|tag:lavfi.signa…
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| /third_party/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_opcode_tmp.h | 153 OP12(UMIN)
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| D | tgsi_info_opcodes.h | 134 OPCODE(1, 2, COMP, UMIN)
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 445 SMIN, SMAX, UMIN, UMAX, enumerator
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| D | TargetLowering.h | 2241 case ISD::UMIN: in isCommutativeBinOp()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 268 case ISD::UMIN: return "umin"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 83 case ISD::UMIN: in PromoteIntegerResult()
730 return DAG.getNode(ISD::UMIN, dl, PromotedType, Add, SatMax); in PromoteIntRes_ADDSUBSAT()
1880 case ISD::UMIN: in ExpandIntegerResult()
2213 return std::make_pair(ISD::SETLT, ISD::UMIN); in getExpandedMinMaxOps()
2214 case ISD::UMIN: in getExpandedMinMaxOps()
2215 return std::make_pair(ISD::SETULT, ISD::UMIN); in getExpandedMinMaxOps()
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| D | LegalizeVectorTypes.cpp | 122 case ISD::UMIN: in ScalarizeVectorResult()
933 case ISD::UMIN: in SplitVectorResult()
2080 case ISD::VECREDUCE_UMIN: CombineOpc = ISD::UMIN; break; in SplitVecOp_VECREDUCE()
2725 case ISD::UMIN: in WidenVectorResult()
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| D | LegalizeVectorOps.cpp | 444 case ISD::UMIN: in LegalizeOp()
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| D | TargetLowering.cpp | 6999 return DAG.getNode(ISD::UMIN, dl, IdxVT, Idx, in clampDynamicVectorIndex()
7108 if (Opcode == ISD::UADDSAT && isOperationLegalOrCustom(ISD::UMIN, VT)) { in expandAddSubSat()
7110 SDValue Min = DAG.getNode(ISD::UMIN, dl, VT, LHS, InvRHS); in expandAddSubSat()
7621 case ISD::VECREDUCE_UMIN: BaseOpcode = ISD::UMIN; break; in expandVecReduce()
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| D | SelectionDAG.cpp | 3336 case ISD::UMIN: { in computeKnownBits()
3724 case ISD::UMIN: in ComputeNumSignBits()
4804 case ISD::UMIN: return C1.ule(C2) ? C1 : C2; in FoldValue()
5201 case ISD::UMIN: in getNode()
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| D | LegalizeDAG.cpp | 3169 case ISD::UMIN: in ExpandNode()
3178 case ISD::UMIN: Pred = ISD::SETULT; break; in ExpandNode()
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| /third_party/mesa3d/src/broadcom/compiler/ |
| D | v3d_compiler.h | 1273 VIR_A_ALU2(UMIN) in VIR_A_ALU2()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 452 setOperationAction(ISD::UMIN, MVT::i16, Legal); in SITargetLowering()
621 setOperationAction(ISD::UMIN, MVT::v2i16, Legal); in SITargetLowering()
649 setOperationAction(ISD::UMIN, MVT::v4i16, Custom); in SITargetLowering()
729 setTargetDAGCombine(ISD::UMIN); in SITargetLowering()
4097 case ISD::UMIN: in LowerOperation()
9032 case ISD::UMIN: in minMaxOpcToMin3Max3Opc()
9191 if (Opc == ISD::UMIN && Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) { in performMinMaxCombine()
9315 case ISD::UMIN: in performExtractVectorEltCombine()
10010 case ISD::UMIN: in PerformDAGCombine()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsScheduleP5600.td | 635 (instregex "^ATOMIC_LOAD_(ADD|SUB|AND|OR|XOR|NAND|MIN|MAX|UMIN|UMAX)"
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| D | MipsSEISelLowering.cpp | 350 setOperationAction(ISD::UMIN, Ty, Legal); in addMSAIntType()
2040 return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2052 return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
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| D | MipsScheduleGeneric.td | 1618 (instregex "^ATOMIC_LOAD_(ADD|SUB|AND|OR|XOR|NAND|MIN|MAX|UMIN|UMAX)"
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 648 setOperationAction(ISD::UMIN, VT, Expand); in initActions()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 186 for (auto Op : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in WebAssemblyTargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 389 def umin : SDNode<"ISD::UMIN" , SDTIntBinOp,
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenFastISel.inc | 2925 // FastEmit functions for ISD::UMIN.
3306 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 194 setOperationAction(ISD::UMIN, VT, Legal); in AArch64TargetLowering()
928 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in addTypeForNEON()
2975 return DAG.getNode(ISD::UMIN, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
12950 ReplaceReductionResults(N, Results, DAG, ISD::UMIN, AArch64ISD::UMINV); in ReplaceNodeResults()
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