| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 40 UXTB, enumerator
60 case AArch64_AM::UXTB: return "uxtb"; in getShiftExtendName()
127 case 0: return AArch64_AM::UXTB; in getExtendType()
154 case AArch64_AM::UXTB: return 0; break; in getExtendEncoding()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 457 UXTB, enumerator
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedPredicates.td | 18 def CheckExtUXTB : CheckImmOperand_s<3, "AArch64_AM::UXTB">;
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| D | AArch64ExpandPseudoInsts.cpp | 637 AArch64_AM::getArithExtendImm(AArch64_AM::UXTB, 0), in expandMI()
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| D | AArch64SchedCyclone.td | 163 // EXAMPLE: ADDXre Xn, Xm, UXTB #1
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| D | AArch64InstructionSelector.cpp | 4739 return AArch64_AM::UXTB; in getExtendTypeForInst()
4762 return !IsLoadStore ? AArch64_AM::UXTB : AArch64_AM::InvalidShiftExtend; in getExtendTypeForInst()
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| D | AArch64ISelDAGToDAG.cpp | 509 return AArch64_AM::UXTB; in getExtendTypeForNode()
527 return !IsLoadStore ? AArch64_AM::UXTB : AArch64_AM::InvalidShiftExtend; in getExtendTypeForNode()
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| D | AArch64InstrInfo.cpp | 790 case AArch64_AM::UXTB: in isFalkorShiftExtFast()
824 case AArch64_AM::UXTB: in isFalkorShiftExtFast()
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| D | AArch64FastISel.cpp | 1173 ExtendType = IsZExt ? AArch64_AM::UXTB : AArch64_AM::SXTB; in emitAddSub()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 306 STORE_OPCODE(ZEXT8, UXTB); in OpcodeCache()
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| D | ARMScheduleSwift.td | 161 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
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| D | ARMScheduleR52.td | 215 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
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| D | ARMExpandPseudoInsts.cpp | 1907 ARM::UXTB, NextMBBI); in ExpandMI()
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| D | ARMScheduleA57.td | 368 // Sign/zero extend, normal: SXTB, SXTH, UXTB, UXTH
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| D | ARMFastISel.cpp | 2906 { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 }
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| D | ARMInstrInfo.td | 3581 def UXTB : AI_ext_rrot<0b01101110,
5908 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
6043 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
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| /third_party/pcre2/pcre2/src/sljit/ |
| D | sljitNativeARM_32.c | 133 #define UXTB 0xe6ef0070 macro
1160 return push_inst(compiler, (op == SLJIT_MOV_U8 ? UXTB : SXTB) | RD(dst) | RM(src2)); in emit_single_op()
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| D | sljitNativeARM_T2_32.c | 180 #define UXTB 0xb2c0 macro
779 return push_inst16(compiler, UXTB | RD3(dst) | RN3(arg2)); in emit_op_imm()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1251 return (ET == AArch64_AM::UXTB || ET == AArch64_AM::SXTB || in isExtend()
1264 return ET == AArch64_AM::UXTB || ET == AArch64_AM::SXTB || in isExtend64()
2750 .Case("uxtb", AArch64_AM::UXTB) in tryParseOptionalShiftExtend()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmWriter.inc | 2581 3214285U, // UXTB
6805 196608U, // UXTB
10980 // SXTB, SXTB16, SXTH, UXTB, UXTB16, UXTH, t2SXTB, t2SXTB16, t2SXTH, t2UX...
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| D | ARMGenMCCodeEmitter.inc | 1889 UINT64_C(116326512), // UXTB
13766 case ARM::UXTB:
18564 CEFBS_IsARM_HasV6, // UXTB = 1876
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| D | ARMGenAsmMatcher.inc | 11560 …{ 1943 /* uxtb */, ARM::UXTB, Convert__Reg1_1__Reg1_2__imm_95_0__CondCode2_0, AMFBS_IsARM, { MCK_C…
11563 …{ 1943 /* uxtb */, ARM::UXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, …
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| D | ARMGenDAGISel.inc | 8745 /* 18300*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::UXTB), 0,
8748 …// Dst: (UXTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (rot_imm_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$r…
8867 /* 18559*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::UXTB), 0,
8870 // Dst: (UXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
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| D | ARMGenInstrInfo.inc | 1891 UXTB = 1876,
7722 …MCID::Predicable), 0x700ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr }, // Inst #1876 = UXTB
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| D | ARMGenGlobalISel.inc | 4870 …// (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 255:{ *:[i32] }) => (UXTB:{ *:[i32] } GPR:{ *:[i32] }:…
4871 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTB,
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