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Searched refs:V128 (Results 1 – 17 of 17) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrSIMD.td23 defm "" : ARGUMENT<V128, v16i8>;
24 defm "" : ARGUMENT<V128, v8i16>;
25 defm "" : ARGUMENT<V128, v4i32>;
26 defm "" : ARGUMENT<V128, v2i64>;
27 defm "" : ARGUMENT<V128, v4f32>;
28 defm "" : ARGUMENT<V128, v2f64>;
45 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
64 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
107 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
112 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
[all …]
DWebAssemblyInstrCall.td63 defm "" : CALL<v16i8, V128, "v128.", [HasSIMD128]>;
64 defm "" : CALL<v8i16, V128, "v128.", [HasSIMD128]>;
65 defm "" : CALL<v4i32, V128, "v128.", [HasSIMD128]>;
66 defm "" : CALL<v2i64, V128, "v128.", [HasSIMD128]>;
67 defm "" : CALL<v4f32, V128, "v128.", [HasSIMD128]>;
68 defm "" : CALL<v2f64, V128, "v128.", [HasSIMD128]>;
DWebAssemblyRegisterInfo.td65 def V128 : WebAssemblyRegClass<[v4f32, v2f64, v2i64, v4i32, v16i8, v8i16], 128,
DWebAssemblyMCInstLower.cpp192 return wasm::ValType::V128; in getType()
DWebAssemblyInstrInfo.td297 defm "" : LOCAL<V128>, Requires<[HasSIMD128]>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td4670 def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128,
4676 def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64,
5151 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b001, opc, V128,
5153 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
5157 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b011, opc, V128,
5159 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
5163 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b101, opc, V128,
5165 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
5166 def v2i64 : BaseSIMDThreeSameVector<1, U, 0b111, opc, V128,
5168 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
[all …]
DAArch64InstrInfo.td805 def : Pat<(v8f16 (int_aarch64_neon_vcadd_rot90 (v8f16 V128:$Rn), (v8f16 V128:$Rm))),
806 (FCADDv8f16 (v8f16 V128:$Rn), (v8f16 V128:$Rm), (i32 0))>;
807 def : Pat<(v8f16 (int_aarch64_neon_vcadd_rot270 (v8f16 V128:$Rn), (v8f16 V128:$Rm))),
808 (FCADDv8f16 (v8f16 V128:$Rn), (v8f16 V128:$Rm), (i32 1))>;
816 def : Pat<(Ty (int_aarch64_neon_vcadd_rot90 (Ty V128:$Rn), (Ty V128:$Rm))),
817 (!cast<Instruction>("FCADD"#Ty) (Ty V128:$Rn), (Ty V128:$Rm), (i32 0))>;
818 def : Pat<(Ty (int_aarch64_neon_vcadd_rot270 (Ty V128:$Rn), (Ty V128:$Rm))),
819 (!cast<Instruction>("FCADD"#Ty) (Ty V128:$Rn), (Ty V128:$Rm), (i32 1))>;
3640 def : Pat<(abs (v8i16 (sub (zext (extract_high_v16i8 V128:$opA)),
3641 (zext (extract_high_v16i8 V128:$opB))))),
[all …]
DAArch64RegisterInfo.td498 def V128 : RegisterOperand<FPR128, "printVRegOperand"> {
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenInstrInfo.inc18866 V128 = 271,
24624 OpTypes::V128, OpTypes::V128,
24627 OpTypes::V128, OpTypes::V128,
24629 OpTypes::V128, OpTypes::V128,
24630 OpTypes::V128, OpTypes::V128,
24647 OpTypes::V64, OpTypes::V128, OpTypes::V128,
24648 OpTypes::V128, OpTypes::V128, OpTypes::V128, OpTypes::V128,
24649 OpTypes::V64, OpTypes::V128, OpTypes::V128,
24650 OpTypes::V128, OpTypes::V128, OpTypes::V128, OpTypes::V128,
24651 OpTypes::V128, OpTypes::V128, OpTypes::V128, OpTypes::V128,
[all …]
DAArch64GenGlobalISel.inc2098 …{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd) => (SABALv2i32_v2i64:{ *:[v2…
2125 …{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd) => (UABALv2i32_v2i64:{ *:[v2…
2152 …V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 370:{ *:[iPTR] }, V6…
2179 …V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 428:{ *:[iPTR] }, V6…
2202 …:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd) => (SMLALv2i32_v2i64:{ *:[v2…
2225 …:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd) => (UMLALv2i32_v2i64:{ *:[v2…
2246 … 371:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd) => (SADALPv4i32_v2i64:{ *:[v…
2266 … 429:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd) => (UADALPv4i32_v2i64:{ *:[v…
2288 …V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 387:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn,…
2311 …V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 441:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn,…
[all …]
DAArch64GenAsmWriter.inc18178 // (INSvi16gpr V128:$dst, VectorIndexH:$idx, GPR32:$src) - 737
18184 // (INSvi16lane V128:$dst, VectorIndexH:$idx, V128:$src, VectorIndexH:$idx2) - 742
18190 // (INSvi32gpr V128:$dst, VectorIndexS:$idx, GPR32:$src) - 747
18196 // (INSvi32lane V128:$dst, VectorIndexS:$idx, V128:$src, VectorIndexS:$idx2) - 752
18202 // (INSvi64gpr V128:$dst, VectorIndexD:$idx, GPR64:$src) - 757
18208 // (INSvi64lane V128:$dst, VectorIndexD:$idx, V128:$src, VectorIndexD:$idx2) - 762
18214 // (INSvi8gpr V128:$dst, VectorIndexB:$idx, GPR32:$src) - 767
18220 // (INSvi8lane V128:$dst, VectorIndexB:$idx, V128:$src, VectorIndexB:$idx2) - 772
20145 // (NOTv16i8 V128:$Vd, V128:$Vn) - 2353
20231 // (ORRv16i8 V128:$dst, V128:$src, V128:$src) - 2421
[all …]
DAArch64GenAsmWriter1.inc18899 // (INSvi16gpr V128:$dst, VectorIndexH:$idx, GPR32:$src) - 737
18905 // (INSvi16lane V128:$dst, VectorIndexH:$idx, V128:$src, VectorIndexH:$idx2) - 742
18911 // (INSvi32gpr V128:$dst, VectorIndexS:$idx, GPR32:$src) - 747
18917 // (INSvi32lane V128:$dst, VectorIndexS:$idx, V128:$src, VectorIndexS:$idx2) - 752
18923 // (INSvi64gpr V128:$dst, VectorIndexD:$idx, GPR64:$src) - 757
18929 // (INSvi64lane V128:$dst, VectorIndexD:$idx, V128:$src, VectorIndexD:$idx2) - 762
18935 // (INSvi8gpr V128:$dst, VectorIndexB:$idx, GPR32:$src) - 767
18941 // (INSvi8lane V128:$dst, VectorIndexB:$idx, V128:$src, VectorIndexB:$idx2) - 772
20866 // (NOTv16i8 V128:$Vd, V128:$Vn) - 2353
20952 // (ORRv16i8 V128:$dst, V128:$src, V128:$src) - 2421
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/MCTargetDesc/
DWebAssemblyMCTargetDesc.cpp149 return wasm::ValType::V128; in toValType()
DWebAssemblyMCTargetDesc.h133 V128 = unsigned(wasm::ValType::V128), enumerator
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/BinaryFormat/
DWasm.h352 V128 = WASM_TYPE_V128, enumerator
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/AsmParser/
DWebAssemblyAsmParser.cpp310 return wasm::ValType::V128; in parseType()
323 .Case("v128", WebAssembly::BlockType::V128) in parseBlockType()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/ObjectYAML/
DWasmYAML.cpp560 ECase(V128); in enumeration()