Searched refs:VALU (Results 1 – 23 of 23) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 18 field bit VALU = 0;
27 // VALU instruction formats.
132 let TSFlags{1} = VALU;
207 …let hasExtraSrcRegAllocReq = !if(VOP1,1,!if(VOP2,1,!if(VOP3,1,!if(VOPC,1,!if(SDWA,1, !if(VALU,1,0)…
223 let VALU = 1;
359 let VALU = 1;
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| D | GCNHazardRecognizer.h | 81 int checkVALUHazards(MachineInstr *VALU);
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| D | SISchedule.td | 54 // FIXME: Should there be a class for instructions which are VALU
55 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
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| D | VOPInstructions.td | 37 let VALU = 1;
115 let VALU = 1;
491 let VALU = 1;
607 let VALU = 1;
667 let VALU = 1;
699 let VALU = 1;
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| D | SIDefines.h | 22 VALU = 1 << 1, enumerator
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| D | SIInstrInfo.h | 342 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
346 return get(Opcode).TSFlags & SIInstrFlags::VALU; in isVALU()
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| D | GCNHazardRecognizer.cpp | 742 int GCNHazardRecognizer::checkVALUHazards(MachineInstr *VALU) { in checkVALUHazards() argument
751 for (const MachineOperand &Def : VALU->defs()) { in checkVALUHazards()
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| D | VOP1Instructions.td | 52 let VALU = 1;
171 let VALU = 1;
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| D | SIInstructions.td | 1092 let AddedComplexity = 1 in { // Prefer SALU to VALU patterns for DAG
1390 // FIXME: This should only be done for VALU inputs
1541 // will be moved to the VALU.
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| D | AMDGPU.td | 81 "Have VALU add/sub instructions without carry out"
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| D | SIInstrInfo.td | 1124 // 32-bit VALU immediate operand that uses the constant bus.
1128 // 32-bit VALU immediate operand with a 16-bit value that uses the
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| D | VOP3Instructions.td | 547 // Only use VALU ops when the result is divergent.
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| D | VOPCInstructions.td | 95 let VALU = 1;
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| D | SOPInstructions.td | 521 // Use added complexity so these patterns are preferred to the VALU patterns.
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| D | VOP2Instructions.td | 73 let VALU = 1;
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| /third_party/mesa3d/src/amd/compiler/ |
| D | README-ISA.md | 217 A VALU instruction or an `s_waitcnt vmcnt(0)` between the two instructions.
222 An SMEM instruction reads an SGPR. Then, a VALU instruction writes that same SGPR.
257 Mitigated by: any VALU instruction except `v_nop`.
262 Any non-VALU instruction reads the EXEC mask. Then, any VALU instruction writes the EXEC mask.
265 A VALU instruction that writes an SGPR (or has a valid SDST operand), or `s_waitcnt_depctr 0xfffe`.
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| D | README.md | 71 …ecial register called `exec` which is used for manually controlling which VALU threads (aka. *lane…
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| /third_party/mesa3d/docs/relnotes/ |
| D | 21.3.3.rst | 103 - aco/optimizer_postRA: Fix combining DPP into VALU.
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| D | 21.3.0.rst | 3554 - aco: combine DPP into VALU before RA
3555 - aco: combine DPP into VALU after RA
3559 - aco: remove label_extract if the extract is used by a non-VALU
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| D | 20.0.0.rst | 2832 - aco: combine two sgprs into a VALU if they're the same
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| D | 20.1.0.rst | 3574 - aco: combine VALU and SALU into various VOP3 instructions
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrAltivec.td | 459 let PPC970_Unit = 5 in { // VALU Operations.
854 } // VALU Operations.
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| /third_party/icu/icu4j/perf-tests/data/collation/ |
| D | TestNames_SerbianSH.txt | 56876 VALUŠEK JOVAN
56877 VALUŠEK KATICA
56878 VALUŠEK PAVLE
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