| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURewriteOutArguments.cpp | 211 VectorType *VT0 = dyn_cast<VectorType>(Ty0); in isVec3ToVec4Shuffle() local
213 if (!VT0 || !VT1) in isVec3ToVec4Shuffle()
216 if (VT0->getNumElements() != 3 || in isVec3ToVec4Shuffle()
220 return DL->getTypeSizeInBits(VT0->getElementType()) == in isVec3ToVec4Shuffle()
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| /third_party/musl/porting/uniproton/kernel/include/bits/ |
| D | termios.h | 77 #define VT0 0000000 macro
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| /third_party/musl/porting/liteos_a_newlib/kernel/include/bits/ |
| D | termios.h | 77 #define VT0 0000000 macro
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| /third_party/musl/porting/liteos_a/kernel/include/bits/ |
| D | termios.h | 77 #define VT0 0000000 macro
|
| /third_party/musl/arch/mips/bits/ |
| D | termios.h | 78 #define VT0 0000000 macro
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| /third_party/musl/arch/powerpc/bits/ |
| D | termios.h | 81 #define VT0 0000000 macro
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| /third_party/musl/arch/mipsn32/bits/ |
| D | termios.h | 78 #define VT0 0000000 macro
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| /third_party/musl/arch/generic/bits/ |
| D | termios.h | 77 #define VT0 0000000 macro
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| /third_party/musl/arch/mips64/bits/ |
| D | termios.h | 78 #define VT0 0000000 macro
|
| /third_party/musl/porting/liteos_m/kernel/include/bits/ |
| D | termios.h | 77 #define VT0 0000000 macro
|
| /third_party/musl/arch/powerpc64/bits/ |
| D | termios.h | 81 #define VT0 0000000 macro
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| /third_party/musl/porting/liteos_m_iccarm/kernel/include/bits/ |
| D | termios.h | 77 #define VT0 0000000 macro
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| /third_party/musl/libc-test/src/api/ |
| D | termios.c | 68 C(VT0) in f()
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| /third_party/python/Modules/ |
| D | termios.c | 530 #ifdef VT0
531 {"VT0", VT0},
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| /third_party/toybox/toys/pending/ |
| D | stty.c | 107 { "bs0", BS0, BSDLY }, { "bs1", BS1, BSDLY }, { "vt0", VT0, VTDLY },
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 75 for (MVT VT0 : MVT::fixedlen_vector_valuetypes()) { in MipsSETargetLowering() local
77 setTruncStoreAction(VT0, VT1, Expand); in MipsSETargetLowering()
78 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
79 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
80 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 3973 EVT VT0 = getSetCCResultType(getSETCCOperandType(SETCC0)); in WidenVSELECTAndMask() local
3975 unsigned ScalarBits0 = VT0.getScalarSizeInBits(); in WidenVSELECTAndMask()
3983 EVT NarrowVT = ((ScalarBits0 < ScalarBits1) ? VT0 : VT1); in WidenVSELECTAndMask()
3984 EVT WideVT = ((NarrowVT == VT0) ? VT1 : VT0); in WidenVSELECTAndMask()
3993 MaskVT = VT0; in WidenVSELECTAndMask()
3996 SETCC0 = convertMask(SETCC0, VT0, MaskVT); in WidenVSELECTAndMask()
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| D | DAGCombiner.cpp | 8509 EVT VT0 = N0.getValueType(); in visitSELECT() local
8518 if (VT == VT0 && VT == MVT::i1 && (N0 == N1 || isOneConstant(N1))) in visitSELECT()
8525 if (VT == VT0 && VT == MVT::i1 && isNullConstant(N1)) { in visitSELECT()
8531 if (VT == VT0 && VT == MVT::i1 && isOneConstant(N2)) { in visitSELECT()
8538 if (VT == VT0 && VT == MVT::i1 && (N0 == N2 || isNullConstant(N2))) in visitSELECT()
8545 if (VT0 == MVT::i1) { in visitSELECT()
8667 SDVTList VTs = DAG.getVTList(VT, VT0); in visitSELECT()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 34536 EVT VT0 = BC0.getValueType(); in combineTargetShuffle() local
34540 if (Opcode0 == Opcode1 && VT0 == VT1 && in combineTargetShuffle()
34552 SDValue Horiz = DAG.getNode(Opcode0, DL, VT0, Lo, Hi); in combineTargetShuffle()
39980 EVT VT0 = Op0.getValueType(); in combineAndMaskToShift() local
39983 if (VT0 != VT1 || !VT0.isSimple() || !VT0.isInteger()) in combineAndMaskToShift()
39995 if (!SupportedVectorShiftWithImm(VT0.getSimpleVT(), Subtarget, ISD::SRL)) in combineAndMaskToShift()
39998 unsigned EltBitWidth = VT0.getScalarSizeInBits(); in combineAndMaskToShift()
40005 SDValue Shift = DAG.getNode(X86ISD::VSRLI, DL, VT0, Op0, ShAmt); in combineAndMaskToShift()
|