Searched refs:VecRC (Results 1 – 5 of 5) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonVExtract.cpp | 139 const auto &VecRC = *MRI.getRegClass(VecR); in runOnMachineFunction() local
140 unsigned Align = HRI.getSpillAlignment(VecRC); in runOnMachineFunction()
146 int FI = MFI.CreateStackObject(HRI.getSpillSize(VecRC), Align, in runOnMachineFunction()
152 unsigned StoreOpc = VecRC.getID() == Hexagon::HvxVRRegClassID in runOnMachineFunction()
161 unsigned VecSize = HRI.getRegSizeInBits(VecRC) / 8; in runOnMachineFunction()
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| D | HexagonVLIWPacketizer.cpp | 871 const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF); in canPromoteToDotNew() local
872 if (DisableVecDblNVStores && VecRC == &Hexagon::HvxWRRegClass) in canPromoteToDotNew()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 3337 const TargetRegisterClass *VecRC = nullptr; in emitINSERT_DF_VIDX() local
3353 VecRC = &Mips::MSA128BRegClass; in emitINSERT_DF_VIDX()
3359 VecRC = &Mips::MSA128HRegClass; in emitINSERT_DF_VIDX()
3365 VecRC = &Mips::MSA128WRegClass; in emitINSERT_DF_VIDX()
3371 VecRC = &Mips::MSA128DRegClass; in emitINSERT_DF_VIDX()
3376 Register Wt = RegInfo.createVirtualRegister(VecRC); in emitINSERT_DF_VIDX()
3394 Register WdTmp1 = RegInfo.createVirtualRegister(VecRC); in emitINSERT_DF_VIDX()
3400 Register WdTmp2 = RegInfo.createVirtualRegister(VecRC); in emitINSERT_DF_VIDX()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 3407 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg); in emitIndirectSrc() local
3411 = computeIndirectRegAndOffset(TRI, VecRC, SrcReg, Offset); in emitIndirectSrc()
3469 const TargetRegisterClass *VecRC) { in getMOVRELDPseudo() argument
3470 switch (TRI.getRegSizeInBits(*VecRC)) { in getMOVRELDPseudo()
3499 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg()); in emitIndirectDst() local
3505 std::tie(SubReg, Offset) = computeIndirectRegAndOffset(TRI, VecRC, in emitIndirectDst()
3539 const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(TRI, VecRC)); in emitIndirectDst()
3557 Register PhiReg = MRI.createVirtualRegister(VecRC); in emitIndirectDst()
3572 const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(TRI, VecRC)); in emitIndirectDst()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 2921 const TargetRegisterClass *VecRC = in emitExtractVectorElt() local
2923 if (!VecRC) { in emitExtractVectorElt()
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