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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonBitTracker.cpp313 uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0; in evaluate() local
325 return rr0(eIMM(im(1), W0), Outputs); in evaluate()
327 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs); in evaluate()
329 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs); in evaluate()
335 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate()
347 uint16_t RW = W0; in evaluate()
356 uint16_t RW = W0; in evaluate()
372 assert(W0 == 64 && W1 == 32); in evaluate()
373 RegisterCell CW = RegisterCell(W0).insert(rc(1), BT::BitMask(0, W1-1)); in evaluate()
381 return rr0(eADD(rc(1), eIMM(im(2), W0)), Outputs); in evaluate()
[all …]
DHexagonVectorPrint.cpp75 || (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) in isVecReg()
185 } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) { in runOnMachineFunction()
186 LLVM_DEBUG(dbgs() << "adding dump for W" << Reg - Hexagon::W0 << '\n'); in runOnMachineFunction()
187 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1, in runOnMachineFunction()
189 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2, in runOnMachineFunction()
DHexagonCallingConv.td89 CCAssignToReg<[W0,W1,W2,W3,W4,W5,W6,W7]>>>,
103 CCAssignToReg<[W0,W1,W2,W3,W4,W5,W6,W7]>>>,
121 CCAssignToReg<[W0]>>>,
129 CCAssignToReg<[W0]>>>,
DHexagonISelLoweringHVX.cpp553 SDValue W0 = isUndef(PredV) in createHvxPrefixPred() local
556 Words[IdxW].push_back(Hi32(W0)); in createHvxPrefixPred()
557 Words[IdxW].push_back(Lo32(W0)); in createHvxPrefixPred()
802 SDValue W0 = extractHvxElementReg(WordVec, W0Idx, dl, MVT::i32, DAG); in extractHvxSubvectorReg() local
804 return DAG.getBitcast(ResTy, W0); in extractHvxSubvectorReg()
808 SDValue WW = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, {W1, W0}); in extractHvxSubvectorReg()
868 SDValue W0 = DAG.getNode(HexagonISD::VEXTRACTW, dl, MVT::i32, {ShuffV, Zero}); in extractHvxSubvectorPred() local
871 SDValue Vec64 = DAG.getNode(HexagonISD::COMBINE, dl, MVT::v8i8, {W1, W0}); in extractHvxSubvectorPred()
/third_party/openssl/crypto/sha/asm/
Dsha512-armv8.pl375 my ($W0,$W1)=("v16.4s","v17.4s");
393 ld1.32 {$W0},[$Ktbl],#16
404 add.i32 $W0,$W0,@MSG[0]
407 sha256h $ABCD,$EFGH,$W0
408 sha256h2 $EFGH,$abcd,$W0
411 ($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG));
415 add.i32 $W0,$W0,@MSG[0]
417 sha256h $ABCD,$EFGH,$W0
418 sha256h2 $EFGH,$abcd,$W0
420 ld1.32 {$W0},[$Ktbl],#16
[all …]
Dsha256-armv4.pl599 my ($W0,$W1,$ABCD_SAVE,$EFGH_SAVE)=map("q$_",(12..15));
624 vld1.32 {$W0},[$Ktbl]!
636 vadd.i32 $W0,$W0,@MSG[0]
639 sha256h $ABCD,$EFGH,$W0
640 sha256h2 $EFGH,$abcd,$W0
643 ($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG));
647 vadd.i32 $W0,$W0,@MSG[0]
649 sha256h $ABCD,$EFGH,$W0
650 sha256h2 $EFGH,$abcd,$W0
652 vld1.32 {$W0},[$Ktbl]!
[all …]
Dsha1-armv8.pl248 my ($W0,$W1)=("v20.4s","v21.4s");
272 add.i32 $W0,@Kxx[0],@MSG[0]
279 sha1c $ABCD,$E,$W0 // 0
280 add.i32 $W0,@Kxx[$j],@MSG[2]
294 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0);
303 sha1p $ABCD,$E0,$W0
Dsha1-armv4-large.pl615 my ($W0,$W1,$ABCD_SAVE)=map("q$_",(12..14));
648 vadd.i32 $W0,@Kxx[0],@MSG[0]
656 sha1c $ABCD,$E,$W0
657 vadd.i32 $W0,@Kxx[$j],@MSG[2]
671 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0);
680 sha1p $ABCD,$E0,$W0
/third_party/iptables/utils/
Dpf.os223 S4:64:1:60:M1360,S,T,N,W0: Linux:google::Linux (Google crawlbot)
225 S2:64:1:60:M*,S,T,N,W0: Linux:2.4::Linux 2.4 (big boy)
226 S3:64:1:60:M*,S,T,N,W0: Linux:2.4:.18-21:Linux 2.4.18 and newer
227 S4:64:1:60:M*,S,T,N,W0: Linux:2.4::Linux 2.4/2.6 <= 2.6.7
228 S4:64:1:60:M*,S,T,N,W0: Linux:2.6:.1-7:Linux 2.4/2.6 <= 2.6.7
242 S20:64:1:60:M*,S,T,N,W0: Linux:2.2:20-25:Linux 2.2.20 and newer
243 S22:64:1:60:M*,S,T,N,W0: Linux:2.2::Linux 2.2
244 S11:64:1:60:M*,S,T,N,W0: Linux:2.2::Linux 2.2
248 S4:64:1:48:M1460,N,W0: Linux:2.4:cluster:Linux 2.4 in cluster
253 T4:64:1:60:M1412,S,T,N,W0: Linux:2.4::Linux 2.4 (late, uncommon)
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/third_party/ffmpeg/libavcodec/mips/
Dwmv2dsp_mmi.c28 #define W0 2048 macro
43 a0 = W0 * b[0] + W0 * b[4]; in wmv2_idct_row_mmi()
47 a4 = W0 * b[0] - W0 * b[4]; in wmv2_idct_row_mmi()
73 a0 = (W0 * b[ 0] + W0 * b[32] ) >> 3; in wmv2_idct_col_mmi()
77 a4 = (W0 * b[ 0] - W0 * b[32] ) >> 3; in wmv2_idct_col_mmi()
/third_party/ffmpeg/libavcodec/
Dwmv2dsp.c26 #define W0 2048 macro
47 a0 = W0 * b[0] + W0 * b[4]; in wmv2_idct_row()
48 a4 = W0 * b[0] - W0 * b[4]; in wmv2_idct_row()
77 a0 = (W0 * b[8 * 0] + W0 * b[8 * 4] ) >> 3; in wmv2_idct_col()
78 a4 = (W0 * b[8 * 0] - W0 * b[8 * 4] ) >> 3; in wmv2_idct_col()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td56 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1], [W0, W1]>>>>>,
92 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
102 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
141 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
144 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
209 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
214 [W0, W1, W2, W3, W4, W5, W6]>>>,
219 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
298 // Handle i1, i8, i16, i32, and i64 passing in register X0 (W0).
300 CCIfType<[i32], CCAssignToRegWithShadow<[W0], [X0]>>,
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DAArch64CollectLOH.cpp262 static_assert(AArch64::W30 - AArch64::W0 + 1 == N_GPR_REGS, "Number of GPRs"); in mapRegToGPRIndex()
265 if (AArch64::W0 <= Reg && Reg <= AArch64::W30) in mapRegToGPRIndex()
266 return Reg - AArch64::W0; in mapRegToGPRIndex()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFCallingConv.td30 CCIfType<[i32], CCAssignToRegWithShadow<[W0], [R0]>>,
31 CCIfType<[i64], CCAssignToRegWithShadow<[R0], [W0]>>
DBPFRegisterInfo.td41 W0, // Return value
/third_party/openssl/crypto/sm3/
Dsm3_local.h50 #define EXPAND(W0,W7,W13,W3,W10) \ argument
51 (P1(W0 ^ W7 ^ ROTATE(W13, 15)) ^ ROTATE(W3, 7) ^ W10)
/third_party/mesa3d/src/intel/isl/
Disl.c1231 uint32_t W0 = phys_level0_sa->w; in isl_calc_phys_slice0_extent_sa_gfx4_2d() local
1235 uint32_t W = isl_minify(W0, l); in isl_calc_phys_slice0_extent_sa_gfx4_2d()
1339 uint32_t W0 = phys_level0_sa->w; in isl_calc_phys_total_extent_el_gfx4_3d() local
1345 uint32_t level_w = isl_align_npot(isl_minify(W0, l), image_align_sa->w); in isl_calc_phys_total_extent_el_gfx4_3d()
1394 const uint32_t W0 = phys_level0_sa->w; in isl_calc_phys_total_extent_el_gfx6_stencil_hiz() local
1407 const uint32_t W = isl_minify(W0, l); in isl_calc_phys_total_extent_el_gfx6_stencil_hiz()
1454 const uint32_t W0 = phys_level0_sa->w; in isl_calc_phys_total_extent_el_gfx9_1d() local
1457 uint32_t W = isl_minify(W0, l); in isl_calc_phys_total_extent_el_gfx9_1d()
2505 const uint32_t W0 = surf->phys_level0_sa.width; in get_image_offset_sa_gfx4_2d() local
2516 uint32_t W = isl_minify(W0, l); in get_image_offset_sa_gfx4_2d()
[all …]
/third_party/vk-gl-cts/framework/delibs/cmake/
DCFlags.cmake77 set(DE_3RD_PARTY_C_FLAGS "${CMAKE_C_FLAGS} ${MSC_BASE_FLAGS} /W0")
78 set(DE_3RD_PARTY_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${MSC_BASE_FLAGS} /EHsc /W0")
/third_party/boost/boost/math/special_functions/detail/
Dlambert_w_lookup_table.ipp32 { // Common to Lambert W0 and W-1 (and exactly representable).
34 }; // halves, 0.5, 0.25, ... 0.000244140625, common to W0 and W-1.
37 { // For Lambert W0 only.
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenCallingConv.inc93 AArch64::W0, AArch64::W1
216 …AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64…
258 …AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64…
460 …AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64…
477 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6
502 …AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64…
915 if (unsigned Reg = State.AllocateReg(AArch64::W0, AArch64::X0)) {
922 if (unsigned Reg = State.AllocateReg(AArch64::X0, AArch64::W0)) {
1055 …AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64…
1071 …AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64…
[all …]
/third_party/boost/libs/nowide/cmake/
DBoostAddWarnings.cmake32 set(warn_off /W0)
/third_party/mesa3d/src/mesa/program/
Dprog_noise.c501 float W0 = l - t; in _mesa_noise4() local
506 float w0 = w - W0; in _mesa_noise4()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/Disassembler/
DBPFDisassembler.cpp112 BPF::W0, BPF::W1, BPF::W2, BPF::W3, BPF::W4, BPF::W5,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h31 case AArch64::X0: return AArch64::W0; in getWRegFromXReg()
71 case AArch64::W0: return AArch64::X0; in getXRegFromWReg()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/Disassembler/
DHexagonDisassembler.cpp498 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) in getSingleInstruction()
499 Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0; in getSingleInstruction()
606 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, in DecodeHvxWRRegisterClass()

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