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Searched refs:XMM1 (Results 1 – 23 of 23) sorted by relevance

/third_party/mesa3d/src/mesa/x86/
Dsse_normal.S77 MOVSS ( M(0), XMM1 ) /* m0 */
79 UNPCKLPS( XMM2, XMM1 ) /* m5 | m0 */
82 MULPS ( XMM0, XMM1 ) /* m5*scale | m0*scale */
88 MULPS ( XMM1, XMM2 ) /* uy*m5*scale | ux*m0*scale */
140 MOVSS ( M(4), XMM1 ) /* m4 */
141 UNPCKLPS( XMM1, XMM0 ) /* m4 | m0 */
147 MOVSS ( M(1), XMM1 ) /* m1 */
149 UNPCKLPS( XMM2, XMM1 ) /* m5 | m1 */
150 MULPS ( XMM4, XMM1 ) /* m5*scale | m1*scale */
168 MULPS ( XMM1, XMM4 ) /* uy*m5 | uy*m1 */
[all …]
Dsse_xform2.S78 MOVAPS( M(4), XMM1 ) /* m7 | m6 | m5 | m4 */
88 MULPS( XMM1, XMM4 ) /* oy*m7 | oy*m6 | oy*m5 | oy*m4 */
193 MOVSS ( M(0), XMM1 ) /* - | - | - | m0 */
195 UNPCKLPS ( XMM2, XMM1 ) /* - | - | m5 | m0 */
202 MULPS ( XMM1, XMM0 ) /* - | - | oy*m5 | ox*m0 */
252 MOVSS ( M(0), XMM1 ) /* - | - | - | m0 */
254 UNPCKLPS ( XMM2, XMM1 ) /* - | - | m5 | m0 */
261 MULPS( XMM1, XMM4 ) /* oy*m5 | ox*m0 */
312 MOVLPS( M(4), XMM1 ) /* m5 | m4 */
323 MULPS( XMM1, XMM4 ) /* oy*m5 | oy*m4 */
[all …]
Dsse_xform3.S79 MOVAPS ( REGOFF(16, EDX), XMM1 ) /* m4 | m5 | m6 | m7 */
94 MULPS ( XMM1, XMM5 ) /* m7*oy | m6*oy | m5*oy | m4*oy */
205 MOVSS ( M(0), XMM1 ) /* - | - | - | m0 */
207 UNPCKLPS ( XMM2, XMM1 ) /* - | - | m5 | m0 */
216 MULPS ( XMM1, XMM0 ) /* - | - | s1*m5 | s0*m0 */
270 MOVSS ( M(0), XMM1 ) /* - | - | - | m0 */
272 UNPCKLPS ( XMM2, XMM1 ) /* - | - | m5 | m0 */
281 MULPS ( XMM1, XMM0 ) /* oy*m5 | ox*m0 */
344 MOVLPS( M(4), XMM1 ) /* m5 | m4 */
354 MULPS ( XMM1, XMM4 ) /* oy*m5 | oy*m4 */
[all …]
Dsse_xform1.S79 MOVAPS( M(12), XMM1 ) /* m15 | m14 | m13 | m12 */
86 ADDPS( XMM1, XMM2 ) /* + | + | + | + */
188 MOVSS( M(12), XMM1 ) /* m12 */
196 ADDSS( XMM1, XMM4 ) /* ox*m0+m12 */
249 MOVSS( M(0), XMM1 ) /* m0 */
255 MULSS( XMM1, XMM3 ) /* ox*m0 */
307 MOVLPS( M(12), XMM1 ) /* m13 | m12 */
314 ADDPS( XMM1, XMM2 ) /* - | - | ox*m1+m13 | ox*m0+m12 */
362 MOVSS( M(12), XMM1 ) /* m12 */
369 ADDSS( XMM1, XMM3 ) /* ox*m0+m12 */
[all …]
Dsse_xform4.S83 MOVSS( SRC(1), XMM1 ) /* oy */
84 SHUFPS( CONST(0x0), XMM1, XMM1 ) /* oy | oy | oy | oy */
85 MULPS( XMM5, XMM1 ) /* oy*m7 | oy*m6 | oy*m5 | oy*m4 */
95 ADDPS( XMM1, XMM0 ) /* ox*m3+oy*m7 | ... */
145 MOVAPS( MAT(4), XMM1 ) /* m7 | m6 | m5 | m4 */
157 MULPS( XMM1, XMM5 ) /* oy*m7 | oy*m6 | oy*m5 | oy*m4 */
Dcommon_x86_asm.S203 MOVUPS ( REGIND( ESP ), XMM1 )
205 DIVPS ( XMM0, XMM1 )
Dassyntax.h225 #define XMM1 %xmm1 macro
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallingConv.td46 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7];
52 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
233 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3
237 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
239 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3
268 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
279 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
280 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
293 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3.
295 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
[all …]
DX86CallingConv.cpp80 static const MCPhysReg RegListXMM[] = {X86::XMM0, X86::XMM1, X86::XMM2, in CC_X86_VectorCallGetSSEs()
DX86CallLowering.cpp165 static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2, in assignArg()
DX86RegisterInfo.td213 def XMM1: X86Reg<"xmm1", 1>, DwarfRegNum<[18, 22, 22]>;
DX86FastISel.cpp3125 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, in fastLowerArguments()
3462 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, in fastLowerCall()
DX86InstrCompiler.td477 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
497 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
DX86ISelLowering.cpp2727 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { in LowerReturn()
3022 if (VA.getLocReg() == X86::XMM1) in LowerCallResult()
3030 if (VA.getLocReg() == X86::XMM1) in LowerCallResult()
3336 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, in get64BitArgumentXMMs()
4009 case X86::XMM1: ShadowReg = X86::RDX; break; in LowerCall()
4066 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, in LowerCall()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenCallingConv.inc232 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
438 X86::XMM0, X86::XMM1, X86::XMM2
603 X86::XMM0, X86::XMM1, X86::XMM2
880 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
904 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1173 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1237 X86::XMM0, X86::XMM1, X86::XMM2
1550 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1688 X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6
1952 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,…
[all …]
DX86GenRegisterInfo.inc164 XMM1 = 144,
1280 { X86::XMM1 },
1586 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,…
1636 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,…
1956 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,…
1986 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,…
2426 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,…
2436 …X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8,…
2733 { 18U, X86::XMM1 },
2810 { 22U, X86::XMM1 },
[all …]
DX86GenInstrInfo.inc16673 …6::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XM…
16674 …6::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, X86::XMM0, X86::XMM1, X86::XMM2, X86::XM…
DX86GenAsmMatcher.inc7205 case X86::XMM1: OpKind = MCK_FR32; break;
/third_party/libffi/src/x86/
Dwin64_intel.S69 movsd XMM1, qword ptr [RSP + 8]; movsd 8(%rsp), %xmm1
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZCallingConv.td74 // Pass in STG registers: XMM1, ..., XMM6
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h220 ENTRY(XMM1) \
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp135 {codeview::RegisterId::XMM1, X86::XMM1}, in initLLVMToSEHAndCVRegMapping()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/DebugInfo/CodeView/
DCodeViewRegisters.def152 CV_REGISTER(XMM1, 155)