Home
last modified time | relevance | path

Searched refs:ZPR (Results 1 – 8 of 8) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td871 def ZPR : ZPRClass<31>;
879 # Width # ", AArch64::ZPR"
894 def ZPRAny : ZPRRegOp<"", ZPRAsmOpAny, ElementSizeNone, ZPR>;
895 def ZPR8 : ZPRRegOp<"b", ZPRAsmOp8, ElementSizeB, ZPR>;
896 def ZPR16 : ZPRRegOp<"h", ZPRAsmOp16, ElementSizeH, ZPR>;
897 def ZPR32 : ZPRRegOp<"s", ZPRAsmOp32, ElementSizeS, ZPR>;
898 def ZPR64 : ZPRRegOp<"d", ZPRAsmOp64, ElementSizeD, ZPR>;
899 def ZPR128 : ZPRRegOp<"q", ZPRAsmOp128, ElementSizeQ, ZPR>;
923 class FPRasZPROperand<int Width> : RegisterOperand<ZPR> {
942 def ZSeqPairs : RegisterTuples<[zsub0, zsub1], [(rotl ZPR, 0), (rotl ZPR, 1)]>;
[all …]
DAArch64SVEInstrInfo.td1101 …def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i32), (SXTW_ZPmZ_D (IMPLICIT_DEF), (PTRUE_D 31), ZPR:…
1102 …def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i16), (SXTH_ZPmZ_D (IMPLICIT_DEF), (PTRUE_D 31), ZPR:…
1103 …def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i8), (SXTB_ZPmZ_D (IMPLICIT_DEF), (PTRUE_D 31), ZPR:…
1104 …def : Pat<(sext_inreg (nxv4i32 ZPR:$Zs), nxv4i16), (SXTH_ZPmZ_S (IMPLICIT_DEF), (PTRUE_S 31), ZPR:…
1105 …def : Pat<(sext_inreg (nxv4i32 ZPR:$Zs), nxv4i8), (SXTB_ZPmZ_S (IMPLICIT_DEF), (PTRUE_S 31), ZPR:…
1106 …def : Pat<(sext_inreg (nxv8i16 ZPR:$Zs), nxv8i8), (SXTB_ZPmZ_H (IMPLICIT_DEF), (PTRUE_H 31), ZPR:…
1108 def : Pat<(nxv16i8 (bitconvert (nxv8i16 ZPR:$src))), (nxv16i8 ZPR:$src)>;
1109 def : Pat<(nxv16i8 (bitconvert (nxv4i32 ZPR:$src))), (nxv16i8 ZPR:$src)>;
1110 def : Pat<(nxv16i8 (bitconvert (nxv2i64 ZPR:$src))), (nxv16i8 ZPR:$src)>;
1111 def : Pat<(nxv16i8 (bitconvert (nxv8f16 ZPR:$src))), (nxv16i8 ZPR:$src)>;
[all …]
DSVEInstrFormats.td3864 def : Pat<(nxv16i1 (setcc (nxv16i8 ZPR:$Zs1),
3867 (!cast<Instruction>(NAME # "_B") (PTRUE_B 31), ZPR:$Zs1, simm5_32b:$imm)>;
3868 def : Pat<(nxv8i1 (setcc (nxv8i16 ZPR:$Zs1),
3871 (!cast<Instruction>(NAME # "_H") (PTRUE_H 31), ZPR:$Zs1, simm5_32b:$imm)>;
3872 def : Pat<(nxv4i1 (setcc (nxv4i32 ZPR:$Zs1),
3875 (!cast<Instruction>(NAME # "_S") (PTRUE_S 31), ZPR:$Zs1, simm5_32b:$imm)>;
3876 def : Pat<(nxv2i1 (setcc (nxv2i64 ZPR:$Zs1),
3879 (!cast<Instruction>(NAME # "_D") (PTRUE_D 31), ZPR:$Zs1, simm5_64b:$imm)>;
3883 (nxv16i8 ZPR:$Zs1),
3885 (!cast<Instruction>(NAME # "_B") PPR_3b:$Pg, ZPR:$Zs1, simm5_32b:$imm)>;
[all …]
DAArch64FrameLowering.cpp1910 enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type; enumerator
1923 case ZPR: in getScale()
1930 bool isScalable() const { return Type == PPR || Type == ZPR; } in isScalable()
1974 RPI.Type = RegPairInfo::ZPR; in computeCalleeSaveRegisterPairs()
2000 case RegPairInfo::ZPR: in computeCalleeSaveRegisterPairs()
2162 case RegPairInfo::ZPR: in spillCalleeSavedRegisters()
2214 if (RPI.Type == RegPairInfo::ZPR || RPI.Type == RegPairInfo::PPR) in spillCalleeSavedRegisters()
2268 case RegPairInfo::ZPR: in restoreCalleeSavedRegisters()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenGlobalISel.inc10868 // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv16i8] }:$src) => ZPR:{ *:[nxv2i64] }:$src
10873 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39,
10882 // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv8i16] }:$src) => ZPR:{ *:[nxv2i64] }:$src
10887 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39,
10896 // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv4i32] }:$src) => ZPR:{ *:[nxv2i64] }:$src
10901 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39,
10910 // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv8f16] }:$src) => ZPR:{ *:[nxv2i64] }:$src
10915 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39,
10924 // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv4f32] }:$src) => ZPR:{ *:[nxv2i64] }:$src
10929 GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC ZPR*/39,
[all …]
DAArch64GenRegisterInfo.inc2668 // ZPR Register Class...
2669 const MCPhysReg ZPR[] = {
2673 // ZPR Bit set.
3476 { ZPR, ZPRBits, 288, 32, sizeof(ZPRBits), AArch64::ZPRRegClassID, 1, true },
5340 { 128, 128, 128, VTLists+39 }, // ZPR
13086 { // ZPR
13087 40, // bsub -> ZPR
13088 40, // dsub -> ZPR
13093 40, // hsub -> ZPR
13100 40, // ssub -> ZPR
[all …]
DAArch64GenInstrInfo.inc19013 ZPR = 418,
DAArch64GenAsmMatcher.inc7502 MCK_ZPR, // register class 'ZPR'