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Searched refs:Zero64 (Results 1 – 4 of 4) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp4492 Register Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass); in extractRsrcPtr() local
4499 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B64), Zero64) in extractRsrcPtr()
4512 .addReg(Zero64) in extractRsrcPtr()
DAMDGPUISelLowering.cpp1699 SDValue Zero64 = DAG.getConstant(0, DL, VT); in LowerUDIVREM64() local
1704 SDValue Neg_RHS = DAG.getNode(ISD::SUB, DL, VT, Zero64, RHS); in LowerUDIVREM64()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp3859 auto Zero64 = MIRBuilder.buildConstant(S64, 0); in lowerU64ToF32BitOps() local
3866 auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64); in lowerU64ToF32BitOps()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp7432 Register Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass); in emitExt128() local
7434 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64) in emitExt128()
7437 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64); in emitExt128()