| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SpeculationHardening.cpp | 233 .addUse(MisspeculatingTaintReg) in insertTrackingCode()
234 .addUse(AArch64::XZR) in insertTrackingCode()
371 .addUse(AArch64::SP) in insertSPToRegTaintPropagation()
377 .addUse(AArch64::XZR) in insertSPToRegTaintPropagation()
378 .addUse(AArch64::XZR) in insertSPToRegTaintPropagation()
394 .addUse(AArch64::SP) in insertRegToSPTaintPropagation()
400 .addUse(TmpReg, RegState::Kill | RegState::Renamable) in insertRegToSPTaintPropagation()
401 .addUse(MisspeculatingTaintReg, RegState::Kill) in insertRegToSPTaintPropagation()
406 .addUse(TmpReg, RegState::Kill) in insertRegToSPTaintPropagation()
454 .addUse(Reg); in makeGPRSpeculationSafe()
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| D | AArch64InstructionSelector.cpp | 756 .addUse(SrcReg) in selectCopy()
1029 .addUse(LHS) in selectCompareBranch()
1129 Shl.addUse(Src2Reg); in selectVectorSHL()
1201 .addUse(ArgsAddrReg) in selectVaStartDarwin()
1202 .addUse(ListReg) in selectVaStartDarwin()
1230 auto MovI = MIB.buildInstr(AArch64::MOVKXi).addDef(DstReg).addUse(SrcReg); in materializeLargeCMVal()
1513 .addUse(CondReg) in select()
1522 .addUse(CondReg) in select()
1761 .addUse(I.getOperand(2).getReg()) in select()
1908 .addUse(LdReg) in select()
[all …]
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| D | AArch64ExpandPseudoInsts.cpp | 295 .addUse(AArch64::WZR) in expandCMP_SWAP_128()
296 .addUse(AArch64::WZR) in expandCMP_SWAP_128()
303 .addUse(StatusReg, RegState::Kill) in expandCMP_SWAP_128()
304 .addUse(StatusReg, RegState::Kill) in expandCMP_SWAP_128()
307 .addUse(StatusReg, getKillRegState(StatusDead)) in expandCMP_SWAP_128()
379 BuildMI(LoopBB, DL, TII->get(AArch64::CBNZX)).addUse(SizeReg).addMBB(LoopBB); in expandSetTagLoop()
520 .addUse(DstReg, RegState::Kill); in expandMI()
693 .addUse(SrcReg) in expandMI()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsInstructionSelector.cpp | 299 .addUse(PseudoMULTuReg); in select()
328 .addUse(Mips::ZERO) in select()
341 .addUse(I.getOperand(2).getReg()) in select()
349 .addUse(I.getOperand(0).getReg()) in select()
350 .addUse(JTIndex); in select()
358 .addUse(DestAddress) in select()
370 .addUse(DestTmp) in select()
371 .addUse(MF.getInfo<MipsFunctionInfo>() in select()
379 .addUse(Dest); in select()
459 .addUse(HILOReg); in select()
[all …]
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| D | MipsCallLowering.cpp | 150 .addUse(PhysReg + (STI.isLittle() ? 0 : 1)) in assignValueToReg()
151 .addUse(PhysReg + (STI.isLittle() ? 1 : 0)) in assignValueToReg()
159 .addUse(PhysReg) in assignValueToReg()
262 .addUse(ValVReg) in assignValueToReg()
270 .addUse(ValVReg) in assignValueToReg()
277 .addUse(ValVReg) in assignValueToReg()
283 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
579 MIB.addUse(CalleeReg); in lowerCall()
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| D | MipsSEISelDAGToDAG.cpp | 135 .addUse(Mips::RA_64, RegState::Undef) in emitMCountABI()
136 .addUse(Mips::ZERO_64); in emitMCountABI()
138 MIB.addUse(Mips::AT_64, RegState::Implicit); in emitMCountABI()
143 .addUse(Mips::RA, RegState::Undef) in emitMCountABI()
144 .addUse(Mips::ZERO); in emitMCountABI()
148 .addUse(Mips::SP) in emitMCountABI()
151 MIB.addUse(Mips::AT, RegState::Implicit); in emitMCountABI()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 1215 .addUse(GetReg) in getSegmentAperture()
1216 .addUse(ShiftAmt.getReg(0)); in getSegmentAperture()
1345 .addUse(Src); in legalizeAddrSpaceCast()
1422 .addUse(Const0.getReg(0)) in extractF64Exponent()
1423 .addUse(Const1.getReg(0)); in extractF64Exponent()
1497 .addUse(CvtHi.getReg(0)) in legalizeITOFP()
1498 .addUse(ThirtyTwo.getReg(0)); in legalizeITOFP()
1604 .addUse(MulVal.getReg(0)) in legalizeSinCos()
1612 .addUse(TrigVal) in legalizeSinCos()
1798 .addUse(PtrReg) in legalizeAtomicCmpXChg()
[all …]
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| D | AMDGPURegisterBankInfo.cpp | 694 .addUse(Reg); in split64BitValueForMapping()
1413 .addUse(VData); in selectStoreIntrinsic()
1416 MIB.addUse(VOffset); in selectStoreIntrinsic()
1418 MIB.addUse(RSrc) in selectStoreIntrinsic()
1419 .addUse(SOffset) in selectStoreIntrinsic()
1443 .addUse(SrcReg); in buildVCopy()
1453 .addUse(SrcReg, 0, AMDGPU::sub0); in buildVCopy()
1456 .addUse(SrcReg, 0, AMDGPU::sub1); in buildVCopy()
1459 .addUse(TmpReg0) in buildVCopy()
1461 .addUse(TmpReg1) in buildVCopy()
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| D | AMDGPUCallLowering.cpp | 63 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
321 Ret.addUse(ReturnAddrVReg); in lowerReturn()
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| D | SIFormMemoryClauses.cpp | 386 B.addUse(R.first, R.second.first & ~RegState::Kill, SubReg); in runOnMachineFunction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/IR/ |
| D | Use.cpp | 27 Val->addUse(*this); in swap()
34 RHS.Val->addUse(RHS); in swap()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 259 return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt); in buildBrIndirect()
268 .addUse(TablePtr) in buildBrJT()
270 .addUse(IndexReg); in buildBrJT()
357 return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest); in buildBrCond()
658 .addUse(Src) in buildInsert()
659 .addUse(Op) in buildInsert()
756 .addUse(Addr) in buildAtomicCmpXchgWithSuccess()
757 .addUse(CmpVal) in buildAtomicCmpXchgWithSuccess()
758 .addUse(NewVal) in buildAtomicCmpXchgWithSuccess()
781 .addUse(Addr) in buildAtomicCmpXchg()
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| D | IRTranslator.cpp | 1134 ICall.addUse(getOrCreateVReg(**AI)); in translateMemFunc()
1197 .addUse(getOrCreateVReg(*CI.getOperand(0))) in translateOverflowIntrinsic()
1198 .addUse(getOrCreateVReg(*CI.getOperand(1))); in translateOverflowIntrinsic()
1373 .addUse(getOrCreateVReg(*Ptr)) in translateKnownIntrinsic()
1513 .addUse(getOrCreateVReg(*CI.getArgOperand(0))); in translateKnownIntrinsic()
1664 MIB.addUse(VRegs[0]); in translateCall()
1868 .addUse(getOrCreateVReg(*U.getOperand(0))) in translateVAArg()
1941 .addUse(getOrCreateVReg(*U.getOperand(0))) in translateShuffleVector()
1942 .addUse(getOrCreateVReg(*U.getOperand(1))) in translateShuffleVector()
2098 MIB.addUse(ValRegs[j]); in finishPendingPhis()
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| D | LegalizerHelper.cpp | 826 .addUse(PtrReg) in narrowScalar()
931 MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1)); in narrowScalar()
1530 .addUse(DstExt) in widenScalar()
1531 .addUse(ShiftAmtReg); in widenScalar()
1951 .addUse(MI.getOperand(1).getReg()) in lower()
1952 .addUse(MI.getOperand(2).getReg()); in lower()
1982 .addUse(LHS) in lower()
1983 .addUse(RHS); in lower()
1996 .addUse(Res) in lower()
1997 .addUse(ShiftAmt); in lower()
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| D | RegBankSelect.cpp | 166 .addUse(Src); in repairReg()
198 MergeBuilder.addUse(SrcReg); in repairReg()
207 UnMergeBuilder.addUse(MO.getReg()); in repairReg()
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| D | CombinerHelper.cpp | 764 MIB.addUse(MI.getOperand(0).getReg()); in applyCombineIndexedLoadStore()
770 MIB.addUse(MatchInfo.Base); in applyCombineIndexedLoadStore()
771 MIB.addUse(MatchInfo.Offset); in applyCombineIndexedLoadStore()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 583 .addUse(LHSReg) in insertComparison()
584 .addUse(RHSReg) in insertComparison()
602 .addUse(PrevRes) in insertComparison()
780 .addUse(CondReg) in selectSelect()
796 .addUse(TrueReg) in selectSelect()
797 .addUse(FalseReg) in selectSelect()
890 .addUse(AndResult) in select()
940 .addUse(SrcReg) in select()
1111 .addUse(OriginalValue) in select()
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| /third_party/flutter/skia/src/gpu/ |
| D | GrResourceAllocator.cpp | 127 intvl->addUse();
143 newIntvl->addUse();
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| D | GrResourceAllocator.h | 195 void addUse() { fUses++; } in addUse() function
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| /third_party/skia/src/gpu/ |
| D | GrResourceAllocator.cpp | 88 intvl->addUse();
96 newIntvl->addUse();
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| D | GrResourceAllocator.h | 220 void addUse() { fUses++; } in addUse() function
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/include/llvm/IR/ |
| D | Value.h | 406 void addUse(Use &U) { U.addToList(&UseList); } in addUse() function
626 if (V) V->addUse(*this); in set()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 126 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
441 MIB.addUse(X86::AL, RegState::Implicit); in lowerCall()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | Value.h | 457 void addUse(Use &U) { U.addToList(&UseList); } in addUse() function
733 if (V) V->addUse(*this); in set()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 148 MIB.addUse(Reg); in addSrcToMIB()
151 MIB.addUse(SrcMIB->getOperand(0).getReg()); in addSrcToMIB()
|