| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_acceleration_structure.c | 722 .align_mul = 2, .align_offset = 0); in get_indices()
730 b, 3, 32, nir_iadd(b, addr, nir_u2u64(b, index_id)), .align_mul = 4, .align_offset = 0); in get_indices()
751 .align_mul = 1, .align_offset = 0); in get_indices()
786 .align_mul = 4, .align_offset = 0), in get_vertices()
805 .align_mul = comp_bytes, .align_offset = 0); in get_vertices()
987 .align_mul = 4, .align_offset = 0), in build_leaf_shader()
992 .align_mul = 4, .align_offset = 0), in build_leaf_shader()
997 .align_mul = 4, .align_offset = 0), in build_leaf_shader()
1015 .write_mask = 15, .align_mul = 16, .align_offset = 0); in build_leaf_shader()
1019 nir_build_store_global(&b, node_id, scratch_addr, .write_mask = 1, .align_mul = 4, in build_leaf_shader()
[all …]
|
| D | radv_query.c | 80 .align_mul = 8); in radv_store_availability()
84 nir_store_ssbo(b, value32, dst_buf, offset, .write_mask = 0x1, .align_mul = 4); in radv_store_availability()
176 nir_ssa_def *load = nir_load_ssbo(&b, 2, 64, src_buf, load_offset, .align_mul = 16); in build_occlusion_query_shader()
210 .align_mul = 8); in build_occlusion_query_shader()
215 .write_mask = 0x1, .align_mul = 8); in build_occlusion_query_shader()
296 nir_ssa_def *available32 = nir_load_ssbo(&b, 1, 32, src_buf, avail_offset, .align_mul = 4); in build_pipeline_statistics_query_shader()
314 nir_ssa_def *start = nir_load_ssbo(&b, 1, 64, src_buf, start_offset, .align_mul = 8); in build_pipeline_statistics_query_shader()
319 nir_ssa_def *end = nir_load_ssbo(&b, 1, 64, src_buf, end_offset, .align_mul = 8); in build_pipeline_statistics_query_shader()
327 .align_mul = 8); in build_pipeline_statistics_query_shader()
332 .write_mask = 0x1, .align_mul = 4); in build_pipeline_statistics_query_shader()
[all …]
|
| D | radv_pipeline_rt.c | 319 nir_load_scratch(b, 1, 32, nir_load_var(b, vars->stack_ptr), .align_mul = 16), 1); in insert_rt_return()
352 nir_build_load_global(b, 1, 32, load_addr, .align_mul = 4, .align_offset = 0); in load_sbt_entry()
397 .align_mul = 64, .align_offset = offset + i * 16); in nir_build_wto_matrix_load()
425 nir_load_var(&b_shader, vars->stack_ptr), .align_mul = 16, in lower_rt_instructions()
452 nir_load_var(&b_shader, vars->stack_ptr), .align_mul = 16, in lower_rt_instructions()
638 .align_mul = 4, .align_offset = 0); in lower_rt_instructions()
650 .align_mul = 64, .align_offset = 16), in lower_rt_instructions()
654 .align_mul = 64, .align_offset = 32), in lower_rt_instructions()
658 .align_mul = 64, .align_offset = 48)}; in lower_rt_instructions()
1267 .align_mul = 4, .align_offset = 0); in insert_traversal_triangle_case()
[all …]
|
| D | radv_meta_copy_vrs_htile.c | 122 nir_ssa_def *input_value = nir_load_ssbo(&b, 1, 32, htile_buf, htile_addr, .align_mul = 4); in build_copy_vrs_htile_shader()
138 .access = ACCESS_NON_READABLE, .align_mul = 4); in build_copy_vrs_htile_shader()
|
| D | radv_meta_buffer.c | 26 .access = ACCESS_NON_READABLE, .align_mul = 16); in build_buffer_fill_shader()
47 nir_ssa_def *load = nir_load_ssbo(&b, 4, 32, src_buf, offset, .align_mul = 16); in build_buffer_copy_shader()
49 .align_mul = 16); in build_buffer_copy_shader()
|
| /third_party/mesa3d/src/compiler/nir/ |
| D | nir_lower_ubo_vec4.c | 93 unsigned align_mul = nir_intrinsic_align_mul(intr); in nir_lower_ubo_vec4_lower() local
102 align_mul = MIN2(align_mul, 16); in nir_lower_ubo_vec4_lower()
107 bool aligned_mul = (align_mul == 16 && in nir_lower_ubo_vec4_lower()
136 } else if (align_mul == 8 && in nir_lower_ubo_vec4_lower()
|
| D | nir_lower_io.c | 1198 uint32_t align_mul, uint32_t align_offset, in build_explicit_io_load() argument
1208 align_mul, align_offset, in build_explicit_io_load()
1216 align_mul, align_offset, in build_explicit_io_load()
1222 align_mul, align_offset, in build_explicit_io_load()
1233 align_mul, align_offset, in build_explicit_io_load()
1240 align_mul, align_offset, in build_explicit_io_load()
1377 nir_intrinsic_set_align(load, align_mul, align_offset); in build_explicit_io_load()
1439 uint32_t align_mul, uint32_t align_offset, in build_explicit_io_store() argument
1448 align_mul, align_offset, in build_explicit_io_store()
1455 align_mul, align_offset, in build_explicit_io_store()
[all …]
|
| D | nir_lower_wrmasks.c | 133 unsigned align_mul = nir_intrinsic_align_mul(intr); in split_wrmask() local
137 align_off = align_off % align_mul; in split_wrmask()
139 nir_intrinsic_set_align(new_intr, align_mul, align_off); in split_wrmask()
|
| D | nir_lower_printf.c | 68 counter->cast.align_mul = 4; in lower_printf_instr()
91 fmt_str_id_deref->cast.align_mul = 4; in lower_printf_instr()
122 dst_arg_deref->cast.align_mul = 4; in lower_printf_instr()
|
| D | nir_opt_load_store_vectorize.c | 176 uint32_t align_mul; member
553 uint32_t align_mul = 31; in calc_alignment() local
556 align_mul = MIN2(align_mul, ffsll(entry->key->offset_defs_mul[i])); in calc_alignment()
559 entry->align_mul = 1u << (align_mul - 1); in calc_alignment()
561 if (!has_align || entry->align_mul >= nir_intrinsic_align_mul(entry->intrin)) { in calc_alignment()
562 entry->align_offset = entry->offset % entry->align_mul; in calc_alignment()
564 entry->align_mul = nir_intrinsic_align_mul(entry->intrin); in calc_alignment()
663 if (!ctx->options->callback(low->align_mul, in new_bitsize_acceptable()
804 first->align_mul = low->align_mul; in vectorize_loads()
890 second->align_mul = low->align_mul; in vectorize_stores()
[all …]
|
| D | nir_deref.c | 883 if (cast->cast.align_mul == 0) in opt_remove_restricting_cast_alignments()
907 if (parent_mul < cast->cast.align_mul) in opt_remove_restricting_cast_alignments()
937 assert(cast->cast.align_mul <= parent_mul); in opt_remove_restricting_cast_alignments()
938 if (parent_offset % cast->cast.align_mul != cast->cast.align_offset) in opt_remove_restricting_cast_alignments()
944 cast->cast.align_mul = 0; in opt_remove_restricting_cast_alignments()
1049 if (cast->cast.align_mul > 0) in opt_replace_struct_wrapper_cast()
1091 if (cast->cast.align_mul > 0) in opt_deref_cast()
1140 parent->cast.align_mul == 0 && in opt_deref_ptr_as_array()
1176 if (cast->cast.align_mul > 0) in is_vector_bitcast_deref()
|
| D | nir_lower_scratch.c | 57 b, intrin->num_components, bit_size == 1 ? 32 : bit_size, offset, .align_mul=align); in lower_load_store()
70 nir_store_scratch(b, value, offset, .align_mul=align, in lower_load_store()
|
| D | nir_opt_memcpy.c | 43 if (cast->cast.align_mul > 0) in opt_memcpy_deref_cast()
|
| D | nir_lower_variable_initializers.c | 186 .align_mul=chunk_size, in nir_zero_initialize_shared_memory()
|
| D | nir_instr_set.c | 175 hash = HASH(hash, instr->cast.align_mul); in hash_deref()
629 deref1->cast.align_mul != deref2->cast.align_mul || in nir_instrs_equal()
|
| D | nir.h | 1585 unsigned align_mul; member
1961 unsigned align_mul, unsigned align_offset) in nir_intrinsic_set_align() argument
1963 assert(util_is_power_of_two_nonzero(align_mul)); in nir_intrinsic_set_align()
1964 assert(align_offset < align_mul); in nir_intrinsic_set_align()
1965 nir_intrinsic_set_align_mul(intrin, align_mul); in nir_intrinsic_set_align()
1979 const unsigned align_mul = nir_intrinsic_align_mul(intrin); in nir_intrinsic_align() local
1981 assert(align_offset < align_mul); in nir_intrinsic_align()
1982 return align_offset ? 1 << (ffs(align_offset) - 1) : align_mul; in nir_intrinsic_align()
4932 uint32_t *align_mul,
5614 typedef bool (*nir_should_vectorize_mem_func)(unsigned align_mul,
|
| /third_party/mesa3d/src/gallium/drivers/etnaviv/tests/ |
| D | lower_ubo_tests.cpp | 143 …nir_load_ubo(&b, 1, 32, index, offset, .align_mul = 16, .align_offset = 0, .range_base = 0, .range… in TEST_F()
158 …nir_load_ubo(&b, 1, 32, index, offset, .align_mul = 16, .align_offset = 0, .range_base = 0, .range… in TEST_F()
175 …nir_load_ubo(&b, 1, 32, index, offset, .align_mul = 16, .align_offset = 0, .range_base = 0, .range… in TEST_F()
|
| /third_party/mesa3d/src/amd/common/ |
| D | ac_nir_lower_ngg.c | 249 …urviving_invocations_in_current_wave), wave_id, .base = lds_addr_base, .align_mul = 1u, .write_mas… in repack_invocations_in_workgroup()
254 …_load_shared(b, 1, num_lds_dwords * 32, nir_imm_int(b, 0), .base = lds_addr_base, .align_mul = 8u); in repack_invocations_in_workgroup()
366 nir_build_store_shared(b, prim_id, addr, .write_mask = 1u, .align_mul = 4u); in emit_ngg_nogs_prim_export()
389 prim_id = nir_build_load_shared(b, 1, 32, addr, .align_mul = 4u); in emit_store_ngg_nogs_es_primitive_id()
697 …(b, es_exporter_tid), es_vertex_lds_addr, .base = lds_es_exporter_tid, .align_mul = 1u, .write_mas… in compact_vertices_after_culling()
701 …nir_build_store_shared(b, pos, exporter_addr, .base = lds_es_pos_x, .align_mul = 4u, .write_mask =… in compact_vertices_after_culling()
706 …store_shared(b, arg_val, exporter_addr, .base = lds_es_arg_0 + 4u * i, .align_mul = 4u, .write_mas… in compact_vertices_after_culling()
724 …d_pos = nir_build_load_shared(b, 4, 32, es_vertex_lds_addr, .base = lds_es_pos_x, .align_mul = 4u); in compact_vertices_after_culling()
729 …ir_build_load_shared(b, 1, 32, es_vertex_lds_addr, .base = lds_es_arg_0 + 4u * i, .align_mul = 4u); in compact_vertices_after_culling()
748 …r_vtx_idx = nir_build_load_shared(b, 1, 8, vtx_addr, .base = lds_es_exporter_tid, .align_mul = 1u); in compact_vertices_after_culling()
[all …]
|
| D | ac_nir_lower_tess_io_to_mem.c | 226 … .align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u); in lower_ls_output_store()
383 … .align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u); in lower_hs_per_vertex_input_load()
421 … .align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u); in lower_hs_output_store()
432 … .align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u); in lower_hs_output_load()
523 … .align_mul = 16u, .align_offset = st->tcs_tess_lvl_out_loc % 16u); in hs_emit_write_tess_factors()
526 … .align_mul = 16u, .align_offset = st->tcs_tess_lvl_in_loc % 16u) in hs_emit_write_tess_factors()
|
| D | ac_nir_lower_esgs_io_to_mem.c | 143 … .align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u); in lower_es_output_store()
217 … .align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u); in lower_gs_per_vertex_input_load()
|
| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_shaderlib_nir.c | 92 nir_ssa_def *value = nir_load_ssbo(&b, 1, 8, zero, src_offset, .align_mul=1); in si_create_dcc_retile_cs()
99 nir_store_ssbo(&b, value, zero, dst_offset, .write_mask=0x1, .align_mul=1); in si_create_dcc_retile_cs()
145 nir_store_ssbo(&b, clear_value, zero, offset, .write_mask=0x1, .align_mul=2); in gfx9_create_clear_dcc_msaa_cs()
|
| /third_party/mesa3d/src/intel/vulkan/ |
| D | anv_nir_lower_ubo_loads.c | 97 .align_mul = nir_intrinsic_align_mul(load), in lower_ubo_load_instr()
107 .align_mul = nir_intrinsic_align_mul(load), in lower_ubo_load_instr()
|
| D | anv_nir_apply_pipeline_layout.c | 266 .align_mul = 8, in build_load_descriptor_mem()
277 .align_mul = 8, in build_load_descriptor_mem()
936 cast->cast.align_mul = ANV_UBO_ALIGNMENT; in lower_load_vulkan_descriptor()
942 cast->cast.align_mul = ANV_SSBO_ALIGNMENT; in lower_load_vulkan_descriptor()
1105 .align_mul = intrin->dest.ssa.bit_size / 8, in lower_load_constant()
|
| /third_party/mesa3d/src/freedreno/ir3/ |
| D | ir3_nir.c | 158 ir3_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset, in ir3_nir_should_vectorize_mem() argument
171 assert(util_is_power_of_two_nonzero(align_mul)); in ir3_nir_should_vectorize_mem()
172 align_mul = MIN2(align_mul, 16); in ir3_nir_should_vectorize_mem()
176 if (align_mul < 4) in ir3_nir_should_vectorize_mem()
179 unsigned worst_start_offset = 16 - align_mul + align_offset; in ir3_nir_should_vectorize_mem()
|
| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_nir_lower_mem_access_bit_sizes.c | 169 const unsigned align_mul = nir_intrinsic_align_mul(intrin); in lower_mem_store_bit_size() local
210 (align_mul >= 4 && (align_offset + start) % 4 == 0) || in lower_mem_store_bit_size()
|