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Searched refs:base_mip (Results 1 – 9 of 9) sorted by relevance

/third_party/mesa3d/src/amd/vulkan/
Dradv_meta_resolve_cs.c816 .mipLevel = src_iview->base_mip, in radv_cmd_buffer_resolve_subpass_cs()
823 .mipLevel = dst_iview->base_mip, in radv_cmd_buffer_resolve_subpass_cs()
892 .baseMipLevel = src_iview->base_mip, in radv_depth_stencil_resolve_subpass_cs()
910 .baseMipLevel = dst_iview->base_mip, in radv_depth_stencil_resolve_subpass_cs()
933 range.baseMipLevel = dst_iview->base_mip; in radv_depth_stencil_resolve_subpass_cs()
Dradv_meta_blit.c249 uint32_t src_width = radv_minify(src_iview->image->info.width, src_iview->base_mip); in meta_emit_blit()
250 uint32_t src_height = radv_minify(src_iview->image->info.height, src_iview->base_mip); in meta_emit_blit()
251 uint32_t src_depth = radv_minify(src_iview->image->info.depth, src_iview->base_mip); in meta_emit_blit()
252 uint32_t dst_width = radv_minify(dest_iview->image->info.width, dest_iview->base_mip); in meta_emit_blit()
253 uint32_t dst_height = radv_minify(dest_iview->image->info.height, dest_iview->base_mip); in meta_emit_blit()
Dradv_meta_resolve.c699 if (radv_layout_dcc_compressed(cmd_buffer->device, dst_img, dest_iview->base_mip, in radv_cmd_buffer_resolve_subpass_hw()
703 .baseMipLevel = dest_iview->base_mip, in radv_cmd_buffer_resolve_subpass_hw()
762 dst_iview->image, dst_iview->base_mip, dst_att.layout, in radv_cmd_buffer_resolve_subpass()
829 dst_iview->base_mip, dest_att.layout, in radv_cmd_buffer_resolve_subpass()
Dradv_meta_clear.c666 if (radv_htile_enabled(iview->image, iview->base_mip) && iview->base_mip == 0 && in depth_view_can_fast_clear()
994 uint32_t last_level = iview->base_mip + iview->level_count - 1; in radv_can_fast_clear_depth()
1027 .baseMipLevel = iview->base_mip, in radv_fast_clear_depth()
1792 cmd_buffer->device, iview->image, iview->base_mip, image_layout, in_render_loop, in radv_can_fast_clear_color()
1817 if (radv_dcc_enabled(iview->image, iview->base_mip)) { in radv_can_fast_clear_color()
1826 uint32_t last_level = iview->base_mip + iview->level_count - 1; in radv_can_fast_clear_color()
1833 uint32_t level = iview->base_mip + l; in radv_can_fast_clear_color()
1860 .baseMipLevel = iview->base_mip, in radv_fast_clear_color()
1881 if (radv_dcc_enabled(iview->image, iview->base_mip)) { in radv_fast_clear_color()
Dradv_image.c1836 hw_level = iview->base_mip; in radv_image_view_make_descriptor()
1849 base_level_info = &plane->surface.u.legacy.zs.stencil_level[iview->base_mip]; in radv_image_view_make_descriptor()
1851 base_level_info = &plane->surface.u.legacy.level[iview->base_mip]; in radv_image_view_make_descriptor()
1857 si_set_mutable_tex_desc_fields(device, image, base_level_info, plane_id, iview->base_mip, in radv_image_view_make_descriptor()
1858 iview->base_mip, blk_w, is_stencil, is_storage_image, in radv_image_view_make_descriptor()
1959 iview->base_mip = range->baseMipLevel; in radv_image_view_init()
Dradv_cmd_buffer.c1730 cmd_buffer->device, image, iview->base_mip, layout, in_render_loop, in radv_emit_fb_color_state()
1824 .baseMipLevel = iview->base_mip, in radv_emit_fb_color_state()
1867 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip); in radv_update_zrange_precision()
2092 .baseMipLevel = iview->base_mip, in radv_update_tc_compat_zrange_metadata()
2117 .baseMipLevel = iview->base_mip, in radv_update_ds_clear_metadata()
2144 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip); in radv_load_ds_clear_metadata()
2308 .baseMipLevel = iview->base_mip, in radv_update_color_clear_metadata()
2314 assert(radv_image_has_cmask(image) || radv_dcc_enabled(image, iview->base_mip)); in radv_update_color_clear_metadata()
2337 if (!radv_image_has_cmask(image) && !radv_dcc_enabled(image, iview->base_mip)) in radv_load_color_clear_metadata()
2349 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip); in radv_load_color_clear_metadata()
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Dradv_device.c6550 if (!radv_dcc_enabled(iview->image, iview->base_mip)) in radv_init_dcc_control_reg()
6634 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip]; in radv_initialise_color_surface()
6643 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false); in radv_initialise_color_surface()
6674 if (radv_dcc_enabled(iview->image, iview->base_mip) && in radv_initialise_color_surface()
6676 va += plane->surface.u.legacy.color.dcc_level[iview->base_mip].dcc_offset; in radv_initialise_color_surface()
6767 if (radv_dcc_enabled(iview->image, iview->base_mip)) in radv_initialise_color_surface()
6789 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip); in radv_initialise_color_surface()
6795 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip); in radv_initialise_color_surface()
6879 unsigned level = iview->base_mip; in radv_initialise_ds_surface()
Dradv_private.h2277 uint32_t base_mip; member
/third_party/mesa3d/docs/relnotes/
D17.2.1.rst68 - radv/gfx9: set descriptor up for base_mip to level range.