Searched refs:cacheline (Results 1 – 13 of 13) sorted by relevance
679 util_cpu_caps.cacheline = sizeof(void *); in util_cpu_detect_once()686 util_cpu_caps.cacheline = 32; in util_cpu_detect_once()692 unsigned int cacheline; in util_cpu_detect_once() local739 cacheline = ((regs2[1] >> 8) & 0xFF) * 8; in util_cpu_detect_once()740 if (cacheline > 0) in util_cpu_detect_once()741 util_cpu_caps.cacheline = cacheline; in util_cpu_detect_once()788 unsigned int cacheline; in util_cpu_detect_once() local790 cacheline = regs2[2] & 0xFF; in util_cpu_detect_once()791 if (cacheline > 0) in util_cpu_detect_once()792 util_cpu_caps.cacheline = cacheline; in util_cpu_detect_once()[all …]
81 unsigned cacheline; member
99 4: @ Get to cacheline (8-word) alignment113 @ Preload trailing part-cacheline, if any
66 - i965: Disallow linear blits that are not cacheline aligned.
41 CPU cacheline size of 0 can be returned by CPUID leaf 0x80000006 in
153 - swr/rast: Correctly allocate SWR_STATS memory as cacheline aligned
136 CPU cacheline size of 0 can be returned by CPUID leaf 0x80000006 in
4004 - intel/isl: Resize clear color buffer to full cacheline
94 unsigned mip_align = MAX2(64, util_get_cpu_caps()->cacheline); in llvmpipe_texture_layout()132 lpr->row_stride[level] = align(nblocksx * block_size, util_get_cpu_caps()->cacheline); in llvmpipe_texture_layout()
137 #define CACHE_SPLIT_CHECK(r0, width, cacheline) \ argument
351 Make sure the instruction which starts a loop does not cross a cacheline355 In the new trace, the hot loop has an instruction which crosses a cacheline358 to grab the bytes from the next cacheline.
405 movd %1, [%2-3] ;to avoid crossing a cacheline
1919 %macro CACHE_SPLIT_CHECK 3 ; address, width, cacheline