Searched refs:dcc_offset (Results 1 – 11 of 11) sorted by relevance
297 uint64_t dcc_offset = tex->surface.meta_offset; in vi_dcc_get_clear_info() local312 dcc_offset += tex->surface.u.gfx9.meta_levels[level].offset; in vi_dcc_get_clear_info()354 dcc_offset += tex->surface.u.legacy.color.dcc_level[level].dcc_offset; in vi_dcc_get_clear_info()358 si_init_buffer_clear(out, dcc_buffer, dcc_offset, clear_size, clear_value); in vi_dcc_get_clear_info()
832 … i, i < tex->surface.num_meta_levels, tex->surface.u.legacy.color.dcc_level[i].dcc_offset, in si_print_texture_info()1069 size = tex->surface.u.legacy.color.dcc_level[i].dcc_offset + in si_texture_create_object()
326 meta_va += tex->surface.u.legacy.color.dcc_level[base_level].dcc_offset; in si_set_mutable_tex_desc_fields()
3219 … cb_dcc_base += tex->surface.u.legacy.color.dcc_level[cb->base.u.tex.level].dcc_offset >> 8; in si_emit_framebuffer_state()
101 uint32_t dcc_offset; /* relative offset within DCC mip tree */ member
677 dcc_level->dcc_offset = 0; in gfx6_compute_level()692 dcc_level->dcc_offset = surf->meta_size; in gfx6_compute_level()694 surf->meta_size = dcc_level->dcc_offset + AddrDccOut->dccRamSize; in gfx6_compute_level()2558 uint64_t dcc_offset = 0; in ac_surface_get_bo_metadata() local2561 dcc_offset = surf->display_dcc_offset ? surf->display_dcc_offset : surf->meta_offset; in ac_surface_get_bo_metadata()2562 assert((dcc_offset >> 8) != 0 && (dcc_offset >> 8) < (1 << 24)); in ac_surface_get_bo_metadata()2566 *tiling_flags |= AMDGPU_TILING_SET(DCC_OFFSET_256B, dcc_offset >> 8); in ac_surface_get_bo_metadata()
751 meta_va += plane->surface.u.legacy.color.dcc_level[base_level].dcc_offset; in si_set_mutable_tex_desc_fields()1265 uint64_t dcc_offset = in radv_init_metadata() local1269 metadata->u.gfx9.dcc_offset_256b = dcc_offset >> 8; in radv_init_metadata()
1494 dcc_level->dcc_offset + dcc_level->dcc_slice_fast_clear_size * range->baseArrayLayer; in radv_clear_dcc()
6676 va += plane->surface.u.legacy.color.dcc_level[iview->base_mip].dcc_offset; in radv_initialise_color_surface()
7434 size = dcc_level->dcc_offset + dcc_fast_clear_size; in radv_init_dcc()
3235 - radeonsi: use vi_dcc_enabled instead of using tex->surface.dcc_offset directly