Searched refs:esgs_ring_size (Results 1 – 12 of 12) sorted by relevance
| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_device.c | 3368 uint32_t esgs_ring_size, struct radeon_winsys_bo *esgs_ring_bo, in fill_geom_tess_rings() argument
3382 desc[2] = esgs_ring_size; in fill_geom_tess_rings()
3400 desc[6] = esgs_ring_size; in fill_geom_tess_rings()
3578 struct radeon_winsys_bo *esgs_ring_bo, uint32_t esgs_ring_size, in radv_emit_gs_ring_sizes() argument
3592 radeon_emit(cs, esgs_ring_size >> 8); in radv_emit_gs_ring_sizes()
3596 radeon_emit(cs, esgs_ring_size >> 8); in radv_emit_gs_ring_sizes()
3741 uint32_t compute_scratch_waves, uint32_t esgs_ring_size, in radv_get_preamble_cs() argument
3803 esgs_ring_size <= queue->esgs_ring_size && gsvs_ring_size <= queue->gsvs_ring_size && in radv_get_preamble_cs()
3809 if (!scratch_size_per_wave && !compute_scratch_size_per_wave && !esgs_ring_size && in radv_get_preamble_cs()
3840 if (esgs_ring_size > queue->esgs_ring_size) { in radv_get_preamble_cs()
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| D | radv_shader.h | 221 uint32_t esgs_ring_size; member
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| D | radv_pipeline.c | 2200 ngg->esgs_ring_size = MIN2(max_esverts, max_gsprims * max_verts_per_prim) * esvert_lds_size * 4; in gfx10_get_ngg_info()
2239 unsigned esgs_ring_size = in radv_pipeline_init_gs_ring_state() local
2244 esgs_ring_size = align(esgs_ring_size, alignment); in radv_pipeline_init_gs_ring_state()
2248 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size); in radv_pipeline_init_gs_ring_state()
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| D | radv_private.h | 672 uint32_t esgs_ring_size; member
1798 unsigned esgs_ring_size; member
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| D | radv_shader.c | 1021 info->ngg_info.esgs_ring_size, in radv_lower_ngg()
1587 sym->size = binary->info.ngg_info.esgs_ring_size; in radv_shader_variant_create()
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| D | radv_cmd_buffer.c | 4925 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed) in radv_CmdBindPipeline()
4926 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size; in radv_CmdBindPipeline()
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_state_shaders.c | 760 out->esgs_ring_size = esgs_lds_size; in gfx9_get_gs_info()
3589 unsigned esgs_ring_size = in si_update_gs_ring_buffers() local
3594 esgs_ring_size = align(esgs_ring_size, alignment); in si_update_gs_ring_buffers()
3597 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size); in si_update_gs_ring_buffers()
3605 bool update_esgs = sctx->chip_class <= GFX8 && esgs_ring_size && in si_update_gs_ring_buffers()
3606 (!sctx->esgs_ring || sctx->esgs_ring->width0 < esgs_ring_size); in si_update_gs_ring_buffers()
3619 esgs_ring_size, sctx->screen->info.pte_fragment_size); in si_update_gs_ring_buffers()
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| D | si_shader.h | 735 unsigned esgs_ring_size; /* in bytes */ member
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| D | si_shader.c | 792 sym->size = shader->gs_info.esgs_ring_size * 4; in si_shader_binary_open()
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| D | gfx10_shader_ngg.c | 2159 shader->gs_info.esgs_ring_size = MIN2(max_esverts, max_gsprims * max_verts_per_prim) * in gfx10_ngg_calculate_subgroup_info()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 20.2.0.rst | 3389 - radeonsi: use the same units for esgs_ring_size and ngg_emit_size
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| D | 20.3.0.rst | 3311 - radeonsi: use the same units for esgs_ring_size and ngg_emit_size
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