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Searched refs:getNamedOperand (Results 1 – 19 of 19) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIPeepholeSDWA.cpp334 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) { in getSrcMods()
335 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) { in getSrcMods()
338 } else if (TII->getNamedOperand(*MI, AMDGPU::OpName::src1) == SrcOp) { in getSrcMods()
339 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers)) { in getSrcMods()
369 MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in convertToSDWA()
370 MachineOperand *SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src0_sel); in convertToSDWA()
372 TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers); in convertToSDWA()
376 Src = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in convertToSDWA()
377 SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src1_sel); in convertToSDWA()
378 SrcMods = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers); in convertToSDWA()
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DGCNDPPCombine.cpp174 auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst); in createDPPInst()
195 if (auto *Mod0 = TII->getNamedOperand(OrigMI, in createDPPInst()
207 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); in createDPPInst()
218 if (auto *Mod1 = TII->getNamedOperand(OrigMI, in createDPPInst()
230 if (auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) { in createDPPInst()
240 if (auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2)) { in createDPPInst()
241 if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) || in createDPPInst()
250 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl)); in createDPPInst()
251 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask)); in createDPPInst()
252 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask)); in createDPPInst()
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DSIFixupVectorISel.cpp177 MachineOperand *Op = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); in fixupGlobalSaddr()
183 bool HasVdst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst) != nullptr; in fixupGlobalSaddr()
184 MachineOperand *VData = TII->getNamedOperand(MI, AMDGPU::OpName::vdata); in fixupGlobalSaddr()
193 NewGlob->addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::offset)); in fixupGlobalSaddr()
195 MachineOperand *Glc = TII->getNamedOperand(MI, AMDGPU::OpName::glc); in fixupGlobalSaddr()
200 MachineOperand *DLC = TII->getNamedOperand(MI, AMDGPU::OpName::dlc); in fixupGlobalSaddr()
204 NewGlob->addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::slc)); in fixupGlobalSaddr()
206 MachineOperand *VDstInOp = TII->getNamedOperand(MI, in fixupGlobalSaddr()
DSILoadStoreOptimizer.cpp289 TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm(); in getOpcodeWidth()
497 DMask = TII.getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm(); in setMI()
504 Format = TII.getNamedOperand(*I, AMDGPU::OpName::format)->getImm(); in setMI()
511 GLC = TII.getNamedOperand(*I, AMDGPU::OpName::glc)->getImm(); in setMI()
513 SLC = TII.getNamedOperand(*I, AMDGPU::OpName::slc)->getImm(); in setMI()
515 DLC = TII.getNamedOperand(*I, AMDGPU::OpName::dlc)->getImm(); in setMI()
665 const auto *TFEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::tfe); in dmasksCanBeCombined()
666 const auto *LWEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::lwe); in dmasksCanBeCombined()
958 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); in mergeRead2Pair()
960 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdst); in mergeRead2Pair()
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DSIAddIMGInit.cpp79 MachineOperand *TFE = TII->getNamedOperand(MI, AMDGPU::OpName::tfe); in runOnMachineFunction()
80 MachineOperand *LWE = TII->getNamedOperand(MI, AMDGPU::OpName::lwe); in runOnMachineFunction()
81 MachineOperand *D16 = TII->getNamedOperand(MI, AMDGPU::OpName::d16); in runOnMachineFunction()
103 TII->getNamedOperand(MI, AMDGPU::OpName::dmask); in runOnMachineFunction()
DSIOptimizeExecMaskingPreRA.cpp112 auto Op = TII.getNamedOperand(MI, AMDGPU::OpName::src1); in getOrNonExecReg()
115 Op = TII.getNamedOperand(MI, AMDGPU::OpName::src0); in getOrNonExecReg()
231 MachineOperand *Op1 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src0); in optimizeVcndVcmpPair()
232 MachineOperand *Op2 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src1); in optimizeVcndVcmpPair()
247 Op1 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src0); in optimizeVcndVcmpPair()
248 Op2 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src1); in optimizeVcndVcmpPair()
249 MachineOperand *CC = TII->getNamedOperand(*Sel, AMDGPU::OpName::src2); in optimizeVcndVcmpPair()
DSIInstrInfo.cpp272 getNamedOperand(LdSt, AMDGPU::OpName::offset); in getMemOperandWithOffset()
275 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr); in getMemOperandWithOffset()
290 getNamedOperand(LdSt, AMDGPU::OpName::offset0); in getMemOperandWithOffset()
292 getNamedOperand(LdSt, AMDGPU::OpName::offset1); in getMemOperandWithOffset()
313 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr); in getMemOperandWithOffset()
326 const MachineOperand *SOffset = getNamedOperand(LdSt, AMDGPU::OpName::soffset); in getMemOperandWithOffset()
330 const MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::vaddr); in getMemOperandWithOffset()
334 const MachineOperand *RSrc = getNamedOperand(LdSt, AMDGPU::OpName::srsrc); in getMemOperandWithOffset()
341 getNamedOperand(LdSt, AMDGPU::OpName::offset); in getMemOperandWithOffset()
347 const MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::vaddr); in getMemOperandWithOffset()
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DSIRegisterInfo.cpp394 MachineOperand *FIOp = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); in resolveFrameIndex()
401 assert(TII->getNamedOperand(MI, AMDGPU::OpName::soffset)->getReg() == in resolveFrameIndex()
405 MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset); in resolveFrameIndex()
590 const MachineOperand *Reg = TII->getNamedOperand(*MI, AMDGPU::OpName::vdata); in buildMUBUFOffsetLoadStore()
597 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)) in buildMUBUFOffsetLoadStore()
598 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)) in buildMUBUFOffsetLoadStore()
607 const MachineOperand *VDataIn = TII->getNamedOperand(*MI, in buildMUBUFOffsetLoadStore()
647 hasAGPRs(RC) ? TII->getNamedOperand(*MI, AMDGPU::OpName::tmp)->getReg() in buildSpillLoadStore()
1027 const MachineOperand *VData = TII->getNamedOperand(*MI, in eliminateFrameIndex()
1029 assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() == in eliminateFrameIndex()
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DSIFoldOperands.cpp615 MachineOperand *SOff = TII->getNamedOperand(*UseMI, AMDGPU::OpName::soffset); in foldOperand()
620 if (TII->getNamedOperand(*UseMI, AMDGPU::OpName::srsrc)->getReg() != in foldOperand()
1014 bool UseCopy = TII->getNamedOperand(*MI, AMDGPU::OpName::src2)->isReg(); in tryConstantFoldOp()
1108 const MachineOperand *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0); in tryFoldInst()
1109 const MachineOperand *Src1 = TII->getNamedOperand(*MI, AMDGPU::OpName::src1); in tryFoldInst()
1270 if (!TII->getNamedOperand(MI, AMDGPU::OpName::clamp)->getImm()) in isClamp()
1274 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in isClamp()
1275 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isClamp()
1287 = TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers)->getImm(); in isClamp()
1289 = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers)->getImm(); in isClamp()
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DAMDGPUMacroFusion.cpp47 const MachineOperand *Src2 = TII.getNamedOperand(SecondMI, in shouldScheduleAdjacent()
DGCNHazardRecognizer.cpp126 const MachineOperand *RegOp = TII->getNamedOperand(RegInstr, in getHWReg()
690 TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in createsVALUHazard()
790 TII->getNamedOperand(*RWLane, AMDGPU::OpName::src1); in checkRWLaneHazards()
893 auto *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0); in fixVcmpxPermlaneHazards()
967 const MachineOperand *SDST = TII->getNamedOperand(*MI, SDSTName); in fixSMEMtoVectorWriteHazards()
1052 if (TII->getNamedOperand(*MI, AMDGPU::OpName::sdst)) in fixVcmpxExecWARHazard()
1146 const auto *Offset = TII->getNamedOperand(*MI, AMDGPU::OpName::offset); in checkNSAtoVMEMHazard()
1341 Register Reg = TII.getNamedOperand(*MI, AMDGPU::OpName::src2)->getReg(); in checkMAIHazards()
DSILowerSGPRSpills.cpp283 TII->getNamedOperand(MI, AMDGPU::OpName::vdata)->getReg(); in runOnMachineFunction()
294 int FI = TII->getNamedOperand(MI, AMDGPU::OpName::addr)->getIndex(); in runOnMachineFunction()
DSIModeRegister.cpp245 unsigned Dst = TII->getNamedOperand(MI, AMDGPU::OpName::simm16)->getImm(); in processBlockPhase1()
266 unsigned Val = TII->getNamedOperand(MI, AMDGPU::OpName::imm)->getImm(); in processBlockPhase1()
DSIShrinkInstructions.cpp743 TII->getNamedOperand(MI, AMDGPU::OpName::src2); in runOnMachineFunction()
756 const MachineOperand *SDst = TII->getNamedOperand(MI, in runOnMachineFunction()
760 const MachineOperand *Src2 = TII->getNamedOperand(MI, in runOnMachineFunction()
DSIInstrInfo.h913 MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
916 const MachineOperand *getNamedOperand(const MachineInstr &MI, in getNamedOperand() function
918 return getNamedOperand(const_cast<MachineInstr &>(MI), OpName); in getNamedOperand()
DSIInsertWaitcnts.cpp642 MachineOperand *MO = TII->getNamedOperand(Inst, AMDGPU::OpName::data); in updateByEvent()
1287 int Imm = TII->getNamedOperand(Inst, AMDGPU::OpName::tgt)->getImm(); in updateEventWaitcntAfter()
DSIFixSGPRCopies.cpp335 TII->getNamedOperand(*MoveImm, AMDGPU::OpName::src0); in isSafeToFoldImmIntoCopy()
DAMDGPUAsmPrinter.cpp864 = TII->getNamedOperand(MI, AMDGPU::OpName::callee); in analyzeResourceUsage()
DSIISelLowering.cpp3132 if (MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0)) in emitGWSMemViolTestLoop()
3308 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx); in loadM0FromVGPR()
3348 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx); in setM0ToIndexFromSGPR()
3404 Register SrcReg = TII->getNamedOperand(MI, AMDGPU::OpName::src)->getReg(); in emitIndirectSrc()
3405 int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm(); in emitIndirectSrc()
3495 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); in emitIndirectDst()
3496 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx); in emitIndirectDst()
3497 const MachineOperand *Val = TII->getNamedOperand(MI, AMDGPU::OpName::val); in emitIndirectDst()
3498 int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm(); in emitIndirectDst()