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Searched refs:getOperand (Results 1 – 25 of 905) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86InstComments.cpp217 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts()
240 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg()); in printMasking()
270 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMA3Comments()
275 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); in printFMA3Comments()
276 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMA3Comments()
281 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMA3Comments()
286 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); in printFMA3Comments()
287 Mul2Name = getRegName(MI->getOperand(1).getReg()); in printFMA3Comments()
292 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMA3Comments()
297 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); in printFMA3Comments()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZAsmPrinter.cpp36 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
37 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
40 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
41 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
42 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
50 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
51 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
54 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
55 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
56 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenMCPseudoLowering.inc19 lowerOperand(MI->getOperand(0), MCOp);
32 lowerOperand(MI->getOperand(0), MCOp);
35 lowerOperand(MI->getOperand(1), MCOp);
38 lowerOperand(MI->getOperand(2), MCOp);
40 lowerOperand(MI->getOperand(3), MCOp);
43 lowerOperand(MI->getOperand(4), MCOp);
47 if (lowerOperand(MI->getOperand(i), MCOp))
57 lowerOperand(MI->getOperand(0), MCOp);
60 lowerOperand(MI->getOperand(1), MCOp);
63 lowerOperand(MI->getOperand(2), MCOp);
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCMIPeephole.cpp167 return MI->getOperand(3).getImm(); in getKnownLeadingZeroCount()
170 MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm()) in getKnownLeadingZeroCount()
171 return MI->getOperand(3).getImm(); in getKnownLeadingZeroCount()
176 MI->getOperand(3).getImm() <= MI->getOperand(4).getImm()) in getKnownLeadingZeroCount()
177 return 32 + MI->getOperand(3).getImm(); in getKnownLeadingZeroCount()
180 uint16_t Imm = MI->getOperand(2).getImm(); in getKnownLeadingZeroCount()
334 int Immed = MI.getOperand(3).getImm(); in simplifyCode()
346 TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI); in simplifyCode()
348 TRI->lookThruCopyLike(MI.getOperand(2).getReg(), MRI); in simplifyCode()
368 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI); in simplifyCode()
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DPPCVSXFMAMutate.cpp112 LIS->getInterval(MI.getOperand(1).getReg()).Query(FMAIdx).valueIn(); in processBlock()
130 Register AddendSrcReg = AddendMI->getOperand(1).getReg(); in processBlock()
132 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) != in processBlock()
138 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg()) in processBlock()
164 if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())) { in processBlock()
186 Register OldFMAReg = MI.getOperand(0).getReg(); in processBlock()
190 Register Reg2 = MI.getOperand(2).getReg(); in processBlock()
191 Register Reg3 = MI.getOperand(3).getReg(); in processBlock()
218 Register KilledProdReg = MI.getOperand(KilledProdOp).getReg(); in processBlock()
219 Register OtherProdReg = MI.getOperand(OtherProdOp).getReg(); in processBlock()
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DPPCPreEmitPeephole.cpp89 if (!BBI->getOperand(1).isImm()) in removeRedundantLIs()
91 assert(BBI->getOperand(0).isReg() && in removeRedundantLIs()
96 Register Reg = BBI->getOperand(0).getReg(); in removeRedundantLIs()
97 int64_t Imm = BBI->getOperand(1).getImm(); in removeRedundantLIs()
99 if (BBI->getOperand(0).isDead()) { in removeRedundantLIs()
100 DeadOrKillToUnset = &BBI->getOperand(0); in removeRedundantLIs()
114 DeadOrKillToUnset = &AfterBBI->getOperand(KillIdx); in removeRedundantLIs()
126 assert(AfterBBI->getOperand(0).isReg() && in removeRedundantLIs()
130 if (!AfterBBI->getOperand(1).isImm() || in removeRedundantLIs()
131 AfterBBI->getOperand(1).getImm() != Imm) in removeRedundantLIs()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenMCPseudoLowering.inc19 lowerOperand(MI->getOperand(0), MCOp);
22 lowerOperand(MI->getOperand(1), MCOp);
25 lowerOperand(MI->getOperand(2), MCOp);
35 lowerOperand(MI->getOperand(0), MCOp);
38 lowerOperand(MI->getOperand(1), MCOp);
41 lowerOperand(MI->getOperand(2), MCOp);
51 lowerOperand(MI->getOperand(0), MCOp);
54 lowerOperand(MI->getOperand(1), MCOp);
57 lowerOperand(MI->getOperand(2), MCOp);
71 lowerOperand(MI->getOperand(0), MCOp);
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600ClauseMergePass.cpp87 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) in getCFAluSize()
94 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled)) in isCFAluEnabled()
111 CFAlu.getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI)); in cleanPotentialDisabledCFAlu()
136 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
137 RootCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
138 (LatrCFAlu.getOperand(KBank0Idx).getImm() != in mergeIfPossible()
139 RootCFAlu.getOperand(KBank0Idx).getImm() || in mergeIfPossible()
140 LatrCFAlu.getOperand(KBank0LineIdx).getImm() != in mergeIfPossible()
141 RootCFAlu.getOperand(KBank0LineIdx).getImm())) { in mergeIfPossible()
152 if (LatrCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVMergeBaseOffset.cpp83 HiLUI.getOperand(1).getTargetFlags() != RISCVII::MO_HI || in detectLuiAddiGlobal()
84 HiLUI.getOperand(1).getType() != MachineOperand::MO_GlobalAddress || in detectLuiAddiGlobal()
85 HiLUI.getOperand(1).getOffset() != 0 || in detectLuiAddiGlobal()
86 !MRI->hasOneUse(HiLUI.getOperand(0).getReg())) in detectLuiAddiGlobal()
88 Register HiLuiDestReg = HiLUI.getOperand(0).getReg(); in detectLuiAddiGlobal()
91 LoADDI->getOperand(2).getTargetFlags() != RISCVII::MO_LO || in detectLuiAddiGlobal()
92 LoADDI->getOperand(2).getType() != MachineOperand::MO_GlobalAddress || in detectLuiAddiGlobal()
93 LoADDI->getOperand(2).getOffset() != 0 || in detectLuiAddiGlobal()
94 !MRI->hasOneUse(LoADDI->getOperand(0).getReg())) in detectLuiAddiGlobal()
106 HiLUI.getOperand(1).setOffset(Offset); in foldOffset()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMInstPrinter.cpp100 const MCOperand &Dst = MI->getOperand(0); in printInst()
101 const MCOperand &MO1 = MI->getOperand(1); in printInst()
102 const MCOperand &MO2 = MI->getOperand(2); in printInst()
103 const MCOperand &MO3 = MI->getOperand(3); in printInst()
123 const MCOperand &Dst = MI->getOperand(0); in printInst()
124 const MCOperand &MO1 = MI->getOperand(1); in printInst()
125 const MCOperand &MO2 = MI->getOperand(2); in printInst()
150 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
164 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
165 MI->getOperand(3).getImm() == -4) { in printInst()
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DARMMCTargetDesc.cpp40 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && in getMCRDeprecationInfo()
41 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && in getMCRDeprecationInfo()
44 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) { in getMCRDeprecationInfo()
45 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) { in getMCRDeprecationInfo()
46 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) { in getMCRDeprecationInfo()
53 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) { in getMCRDeprecationInfo()
60 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 && in getMCRDeprecationInfo()
61 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) { in getMCRDeprecationInfo()
71 if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() && in getITDeprecationInfo()
72 MI.getOperand(1).getImm() != 8) { in getITDeprecationInfo()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRExpandPseudoInsts.cpp145 Register DstReg = MI.getOperand(0).getReg(); in expandArith()
146 Register SrcReg = MI.getOperand(2).getReg(); in expandArith()
147 bool DstIsDead = MI.getOperand(0).isDead(); in expandArith()
148 bool DstIsKill = MI.getOperand(1).isKill(); in expandArith()
149 bool SrcIsKill = MI.getOperand(2).isKill(); in expandArith()
150 bool ImpIsDead = MI.getOperand(3).isDead(); in expandArith()
165 MIBHI->getOperand(3).setIsDead(); in expandArith()
168 MIBHI->getOperand(4).setIsKill(); in expandArith()
178 Register DstReg = MI.getOperand(0).getReg(); in expandLogic()
179 Register SrcReg = MI.getOperand(2).getReg(); in expandLogic()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreISelDAGToDAG.cpp97 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) in SelectADDRspii()
98 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRspii()
128 OutOps.push_back(Op.getOperand(0)); in SelectInlineAsmMemoryOperand()
163 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
164 N->getOperand(2) }; in Select()
170 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
171 N->getOperand(2) }; in Select()
177 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
178 N->getOperand(2), N->getOperand(3) }; in Select()
184 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCCompound.cpp96 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
97 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
98 Src2Reg = MI.getOperand(2).getReg(); in getCompoundCandidateGroup()
110 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
111 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
122 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
123 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
132 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
141 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
142 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
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DHexagonMCDuplexInfo.cpp202 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
203 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
220 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
221 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
241 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
242 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
251 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
252 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
261 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
262 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsMCCodeEmitter.cpp62 assert(Inst.getOperand(2).isImm()); in LowerLargeShift()
64 int64_t Shift = Inst.getOperand(2).getImm(); in LowerLargeShift()
70 Inst.getOperand(2).setImm(Shift); in LowerLargeShift()
95 unsigned RegOp0 = Inst.getOperand(0).getReg(); in LowerCompactBranch()
96 unsigned RegOp1 = Inst.getOperand(1).getReg(); in LowerCompactBranch()
116 Inst.getOperand(0).setReg(RegOp1); in LowerCompactBranch()
117 Inst.getOperand(1).setReg(RegOp0); in LowerCompactBranch()
239 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValue()
261 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValue1SImm16()
283 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValueMMR6()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp819 LHS = N.getOperand(0); in isSetCCEquivalent()
820 RHS = N.getOperand(1); in isSetCCEquivalent()
821 CC = N.getOperand(2); in isSetCCEquivalent()
826 !TLI.isConstTrueVal(N.getOperand(2).getNode()) || in isSetCCEquivalent()
827 !TLI.isConstFalseVal(N.getOperand(3).getNode())) in isSetCCEquivalent()
834 LHS = N.getOperand(0); in isSetCCEquivalent()
835 RHS = N.getOperand(1); in isSetCCEquivalent()
836 CC = N.getOperand(4); in isSetCCEquivalent()
905 auto *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); in reassociationCanBreakAddressingModePattern()
958 if (SDNode *C1 = DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1))) { in reassociateOpsCommutative()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.cpp172 if (Opc == EndLoopOp && I->getOperand(0).getMBB() != TargetBB) in findLoopInstr()
191 const MachineOperand &MO = MI.getOperand(i); in parseOperands()
254 const MachineOperand OpFI = MI.getOperand(1); in isLoadFromStackSlot()
257 const MachineOperand OpOff = MI.getOperand(2); in isLoadFromStackSlot()
261 return MI.getOperand(0).getReg(); in isLoadFromStackSlot()
268 const MachineOperand OpFI = MI.getOperand(2); in isLoadFromStackSlot()
271 const MachineOperand OpOff = MI.getOperand(3); in isLoadFromStackSlot()
275 return MI.getOperand(0).getReg(); in isLoadFromStackSlot()
302 const MachineOperand &OpFI = MI.getOperand(0); in isStoreToStackSlot()
305 const MachineOperand &OpOff = MI.getOperand(1); in isStoreToStackSlot()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiInstPrinter.cpp49 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
51 (MI->getOperand(2).getImm() == AddOffset || in usesGivenOffset()
52 MI->getOperand(2).getImm() == -AddOffset); in usesGivenOffset()
56 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
61 unsigned AluCode = MI->getOperand(3).getImm(); in isPostIncrementForm()
66 if (MI->getOperand(2).getImm() < 0) in decIncOperator()
77 << getRegisterName(MI->getOperand(1).getReg()) << "], %" in printMemoryLoadIncrement()
78 << getRegisterName(MI->getOperand(0).getReg()); in printMemoryLoadIncrement()
83 << getRegisterName(MI->getOperand(1).getReg()) << decIncOperator(MI) in printMemoryLoadIncrement()
84 << "], %" << getRegisterName(MI->getOperand(0).getReg()); in printMemoryLoadIncrement()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp419 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0)); in lowerSELECT()
420 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1), in lowerSELECT()
421 Op->getOperand(2)); in lowerSELECT()
488 SDValue Op0 = N->getOperand(0); in performANDCombine()
489 SDValue Op1 = N->getOperand(1); in performANDCombine()
508 SDValue Op0Op2 = Op0->getOperand(2); in performANDCombine()
515 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 }; in performANDCombine()
558 N = N->getOperand(0); in isVectorAllOnes()
582 if (isVectorAllOnes(N->getOperand(0))) in isBitwiseInverse()
583 return N->getOperand(1) == OfNode; in isBitwiseInverse()
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DMipsInstructionSelector.cpp101 Register DstReg = I.getOperand(0).getReg(); in selectCopy()
178 const Register ValueReg = I.getOperand(0).getReg(); in selectLoadStoreOpCode()
265 isRegInGprb(I.getOperand(0).getReg(), MRI)) { in select()
267 .add(I.getOperand(0)) in select()
268 .add(I.getOperand(1)) in select()
269 .add(I.getOperand(2)); in select()
272 Mul->getOperand(3).setIsDead(true); in select()
273 Mul->getOperand(4).setIsDead(true); in select()
292 .add(I.getOperand(1)) in select()
293 .add(I.getOperand(2)); in select()
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DMicroMipsSizeReduction.cpp310 if (!MI->getOperand(Op).isImm()) in GetImm()
312 Imm = MI->getOperand(Op).getImm(); in GetImm()
364 Register reg = MI->getOperand(0).getReg(); in CheckXWPInstr()
371 if (ReduceToLwp && (MI->getOperand(0).getReg() == MI->getOperand(1).getReg())) in CheckXWPInstr()
406 Register Reg1 = MI1->getOperand(0).getReg(); in ConsecutiveInstr()
407 Register Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr()
448 if (!IsSP(MI->getOperand(1))) in ReduceXWtoXWSP()
478 Register Reg1 = MI1->getOperand(1).getReg(); in ReduceXWtoXWP()
479 Register Reg2 = MI2->getOperand(1).getReg(); in ReduceXWtoXWP()
500 if (!isMMThreeBitGPRegister(MI->getOperand(0)) || in ReduceArithmeticInstructions()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCInstPrinter.cpp76 MI->getOperand(2).isExpr()) { in printInst()
77 assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) && in printInst()
81 assert(isa<MCSymbolRefExpr>(MI->getOperand(2).getExpr()) && in printInst()
97 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
98 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
99 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
120 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { in printInst()
131 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
132 unsigned char ME = MI->getOperand(3).getImm(); in printInst()
154 unsigned char TH = MI->getOperand(0).getImm(); in printInst()
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DPPCMCCodeEmitter.cpp46 const MCOperand &MO = MI.getOperand(OpNo); in getDirectBrEncoding()
58 const MCOperand &MO = MI.getOperand(OpNo); in getCondBrEncoding()
71 const MCOperand &MO = MI.getOperand(OpNo); in getAbsDirectBrEncoding()
84 const MCOperand &MO = MI.getOperand(OpNo); in getAbsCondBrEncoding()
96 const MCOperand &MO = MI.getOperand(OpNo); in getImm16Encoding()
110 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIEncoding()
111 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16; in getMemRIEncoding()
113 const MCOperand &MO = MI.getOperand(OpNo); in getMemRIEncoding()
128 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIXEncoding()
129 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14; in getMemRIXEncoding()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstructionSelector.cpp434 LLT Ty = MRI.getType(I.getOperand(0).getReg()); in unsupportedBinOp()
587 const Register DstReg = I.getOperand(0).getReg(); in isValidCopy()
588 const Register SrcReg = I.getOperand(1).getReg(); in isValidCopy()
629 MachineOperand &RegOp = I.getOperand(1); in selectSubregisterCopy()
634 if (!Register::isPhysicalRegister(I.getOperand(0).getReg())) in selectSubregisterCopy()
635 RBI.constrainGenericRegister(I.getOperand(0).getReg(), *To, MRI); in selectSubregisterCopy()
648 Register DstReg = I.getOperand(0).getReg(); in getRegClassesForCopy()
649 Register SrcReg = I.getOperand(1).getReg(); in getRegClassesForCopy()
674 Register DstReg = I.getOperand(0).getReg(); in selectCopy()
675 Register SrcReg = I.getOperand(1).getReg(); in selectCopy()
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