| /third_party/skia/experimental/sorttoy/ |
| D | Fake.cpp | 141 void FakeDevice::getOrder(std::vector<ID>* ops) const { in getOrder() function in FakeDevice
184 std::vector<ID> FakeCanvas::getOrder() const { in getOrder() function in FakeCanvas
190 d->getOrder(&ops); in getOrder()
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| D | Fake.h | 219 void getOrder(std::vector<ID>*) const;
269 std::vector<ID> getOrder() const;
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| D | sorttoy.cpp | 271 std::vector<ID> actualOrder = fake.getOrder(); in sort_test()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SDNodeDbgValue.h | 121 unsigned getOrder() const { return Order; } in getOrder() function
161 unsigned getOrder() const { return Order; } in getOrder() function
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| D | ScheduleDAGSDNodes.cpp | 745 unsigned DVOrder = DV->getOrder(); in ProcessSDDbgValues()
943 return LHS->getOrder() < RHS->getOrder(); in EmitSchedule()
956 if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order) in EmitSchedule()
982 assert((*DI)->getOrder() >= LastOrder && in EmitSchedule()
1004 (*DLI)->getOrder() >= LastOrder && (*DLI)->getOrder() < Order; in EmitSchedule()
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| D | SelectionDAGDumper.cpp | 773 OS << " DbgVal(Order=" << getOrder() << ')'; in print()
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| D | SelectionDAG.cpp | 8211 std::max(ToNode->getIROrder(), Dbg->getOrder())); in transferDbgValues()
8251 DV->isIndirect(), DV->getDebugLoc(), DV->getOrder()); in salvageDebugInfo()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | AllocationOrder.cpp | 36 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in AllocationOrder()
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| D | AllocationOrder.h | 49 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder() function
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| D | RegAllocBase.cpp | 137 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); in allocatePhysRegs()
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| D | BreakFalseDeps.cpp | 144 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
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| D | RegAllocFast.cpp | 716 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtReg()
763 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtRegUndef()
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| D | RegAllocGreedy.cpp | 1032 for (auto PhysReg : Order.getOrder()) { in getCheapestEvicteeWeight()
1118 unsigned OrderLimit = Order.getOrder().size(); in tryEvict()
1137 if (TRI->getCostPerUse(Order.getOrder().back()) >= CostPerUseLimit) { in tryEvict()
1550 for (auto PhysReg : Order.getOrder()) { in splitCanCauseLocalSpill()
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| D | CriticalAntiDepBreaker.cpp | 407 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister()
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| D | AggressiveAntiDepBreaker.cpp | 632 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 96 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder() function
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| /third_party/icu/icu4c/source/test/intltest/ |
| D | ssearch.cpp | 353 int32_t getOrder(int32_t index) const;
466 int32_t OrderList::getOrder(int32_t index) const in getOrder() function in OrderList
519 if (getOrder(i) != other.getOrder(j)) { in matchesAt()
1230 targetOrders.getOrder(i + patternSize) != UCOL_NULLORDER) { in simpleSearch()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIPreAllocateWWMRegs.cpp | 107 for (unsigned PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { in processDef()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64A57FPLoadBalancing.cpp | 519 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 587 for (unsigned Reg : RegClassInfo.getOrder(&RegClass)) in findFreeReg()
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