| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 95 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValPredInSU()
133 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValSuccInSU()
329 && TLI->getRegClassFor(VT) in rawRegPressureDelta()
330 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
340 if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT) in rawRegPressureDelta()
341 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
478 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode()
489 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode()
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| D | InstrEmitter.cpp | 108 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg()
167 DstRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg()
210 const TargetRegisterClass *VTRC = TLI->getRegClassFor( in CreateVirtualRegisters()
273 const TargetRegisterClass *RC = TLI->getRegClassFor( in getVR()
383 ? TLI->getRegClassFor(OpVT, in AddOperand()
465 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx); in ConstrainForSubReg()
500 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent()); in EmitSubregNode()
570 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent()); in EmitSubregNode()
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| D | FastISel.cpp | 445 Reg = createResultReg(TLI.getRegClassFor(VT)); in materializeConstant()
942 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64)); in selectPatchpoint()
1552 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT); in selectBitCast()
1553 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT); in selectBitCast()
2232 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in fastEmitInst_extractsubreg()
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| D | FunctionLoweringInfo.cpp | 359 MF->getSubtarget().getTargetLowering()->getRegClassFor(VT, isDivergent)); in CreateReg()
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| D | SelectionDAGISel.cpp | 1250 TLI->getRegClassFor(TLI->getPointerTy(CurDAG->getDataLayout())); in PrepareEHLandingPad()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | SwiftErrorValueTracking.cpp | 36 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVReg()
58 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVRegDefAt()
126 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in createEntriesInEntryBlock()
241 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in propagateVRegs()
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| D | CallingConvLower.cpp | 251 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
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| D | MachineScheduler.cpp | 2761 TLI->getRegClassFor(LegalIntVT)); in initPolicy()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 401 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToFPReg()
411 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToIntReg()
437 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
453 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
517 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeInt()
610 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
624 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
675 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); in fastMaterializeAlloca()
981 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
993 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
[all …]
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| D | ARMISelLowering.h | 482 getRegClassFor(MVT VT, bool isDivergent = false) const override;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 468 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); in X86FastEmitLoad()
2025 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitCMoveSelect()
2200 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitSSESelect()
2352 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitPseudoSelect()
2380 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86SelectSelect()
2450 const TargetRegisterClass *RC = TLI.getRegClassFor(DstVT); in X86SelectIntToFP()
2510 return X86SelectFPExtOrFPTrunc(I, Opc, TLI.getRegClassFor(MVT::f64)); in X86SelectFPExt()
2524 return X86SelectFPExtOrFPTrunc(I, Opc, TLI.getRegClassFor(MVT::f32)); in X86SelectFPTrunc()
2626 const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::v8i16); in fastLowerIntrinsicCall()
2838 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); in fastLowerIntrinsicCall()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1634 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitSignExtendToI32InReg()
1653 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitAtomicBinaryPartword()
1656 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); in emitAtomicBinaryPartword()
1849 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); in emitAtomicCmpSwap()
1901 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitAtomicCmpSwapPartword()
1904 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); in emitAtomicCmpSwapPartword()
2527 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); in lowerRETURNADDR()
3652 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
3719 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); in LowerFormalArguments()
4057 RC = getRegClassFor(VT); in parseRegForInlineAsmConstraint()
[all …]
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| D | MipsSEISelDAGToDAG.cpp | 1191 TLI->getRegClassFor(ViaVecTy.getSimpleVT()); in trySelect()
1260 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple); in trySelect()
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| D | MipsFastISel.cpp | 1300 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); in finishCall()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 414 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm); in materializeFP()
427 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
447 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
562 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true); in fastMaterializeFloatZero()
2945 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg, in selectIntToFP()
3178 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); in finishCall()
3646 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
3820 ResultReg1 = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.h | 405 getRegClassFor(MVT VT, bool isDivergent) const override;
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| D | SIISelLowering.cpp | 4575 …unsigned Reg = MF.addLiveIn(TRI->getReturnAddressReg(MF), getRegClassFor(VT, Op.getNode()->isDiver… in LowerRETURNADDR()
10376 getRegClassFor(VT, Src0.getNode()->isDivergent()); in PostISelFolding()
10993 SITargetLowering::getRegClassFor(MVT VT, bool isDivergent) const { in getRegClassFor() function in SITargetLowering
10994 const TargetRegisterClass *RC = TargetLoweringBase::getRegClassFor(VT, false); in getRegClassFor()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.cpp | 516 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); in LowerCCCArguments()
1071 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 567 const TargetRegisterClass *RC = getRegClassFor(MVT::i64); in EmitSubregExt()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 1521 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT); in finishCall()
1526 ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in finishCall()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 712 getRegClassFor(MVT::i16)); in LowerCCCArguments()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 944 MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrVT)); in LowerFormalArguments()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 792 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
1041 unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 601 getRegClassFor(VA.getLocVT())); in LowerFormalArguments_64()
2673 unsigned RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT)); in LowerRETURNADDR()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetLowering.h | 707 virtual const TargetRegisterClass *getRegClassFor(MVT VT, bool isDivergent = false) const {
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