| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 299 if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) { in getCommonSuperRegClass()
307 unsigned MinSize = getRegSizeInBits(*RCA); in getCommonSuperRegClass()
315 if (!RC || getRegSizeInBits(*RC) < MinSize) in getCommonSuperRegClass()
324 if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC)) in getCommonSuperRegClass()
333 if (getRegSizeInBits(*BestRC) == MinSize) in getCommonSuperRegClass()
472 unsigned TargetRegisterInfo::getRegSizeInBits(unsigned Reg, in getRegSizeInBits() function in TargetRegisterInfo
491 return getRegSizeInBits(*RC); in getRegSizeInBits()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 135 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
142 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
149 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
156 getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
170 if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC)) in getLargestLegalSuperClass()
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| D | X86CallLowering.cpp | 136 MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI); in assignValueToReg()
270 MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI); in assignValueToReg()
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| D | X86SpeculativeLoadHardening.cpp | 750 int PredStateSizeInBytes = TRI->getRegSizeInBits(*PS->RC) / 8; in tracePredStateThroughCFG()
1176 int PredStateSizeInBytes = TRI->getRegSizeInBits(*PS->RC) / 8; in tracePredStateThroughIndirectBranches()
1939 .addImm(TRI->getRegSizeInBits(*PS->RC) - 1); in extractPredStateFromSP()
2239 int RegBytes = TRI->getRegSizeInBits(*RC) / 8; in canHardenRegister()
2287 int Bytes = TRI->getRegSizeInBits(*RC) / 8; in hardenValueInRegister()
2557 int PredStateSizeInBytes = TRI->getRegSizeInBits(*PS->RC) / 8; in tracePredStateThroughCall()
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| D | X86FlagsCopyLowering.cpp | 998 int OrigRegSize = TRI->getRegSizeInBits(OrigRC) / 8; in rewriteSetCarryExtended()
999 int TargetRegSize = TRI->getRegSizeInBits(SetBRC) / 8; in rewriteSetCarryExtended()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrInfo.cpp | 40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.cpp | 351 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64))) in shouldCoalesce()
358 unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0); in shouldCoalesce()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBank.cpp | 52 assert(getSize() >= TRI.getRegSizeInBits(SubRC) && in verify()
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| D | InstructionSelect.cpp | 208 if (Ty.isValid() && Ty.getSizeInBits() > TRI.getRegSizeInBits(*RC)) { in runOnMachineFunction()
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| D | RegisterBankInfo.cpp | 504 return TRI.getRegSizeInBits(*RC); in getSizeInBits()
506 return TRI.getRegSizeInBits(Reg, MRI); in getSizeInBits()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNRegPressure.cpp | 91 (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE) : in getRegKind()
93 (STI->getRegSizeInBits(*RC) == 32 ? AGPR32 : AGPR_TUPLE) : in getRegKind()
94 (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE); in getRegKind()
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| D | SIRegisterInfo.cpp | 1274 unsigned Size = getRegSizeInBits(*RC); in hasVGPRs()
1301 unsigned Size = getRegSizeInBits(*RC); in hasAGPRs()
1327 switch (getRegSizeInBits(*SRC)) { in getEquivalentVGPRClass()
1353 switch (getRegSizeInBits(*SRC)) { in getEquivalentAGPRClass()
1371 switch (getRegSizeInBits(*VRC)) { in getEquivalentSGPRClass()
1708 unsigned SrcSize = getRegSizeInBits(*SrcRC); in shouldCoalesce()
1709 unsigned DstSize = getRegSizeInBits(*DstRC); in shouldCoalesce()
1710 unsigned NewSize = getRegSizeInBits(*NewRC); in shouldCoalesce()
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| D | GCNRegBankReassign.cpp | 282 unsigned Size = TRI->getRegSizeInBits(*RC); in getPhysRegBank()
309 unsigned Size = TRI->getRegSizeInBits(*RC) / 32; in getRegBankMask()
446 unsigned Size = TRI->getRegSizeInBits(*RC); in isReassignable()
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| D | SIAddIMGInit.cpp | 127 RI->getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32; in runOnMachineFunction()
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| D | SILowerI1Copies.cpp | 106 TII->getRegisterInfo().getRegSizeInBits(Reg, *MRI) == in isLaneMaskReg()
497 unsigned Size = TRI.getRegSizeInBits(Reg, MRI); in isVRegCompatibleReg()
703 assert(TII->getRegisterInfo().getRegSizeInBits(SrcReg, *MRI) == 32); in lowerCopiesToI1()
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| D | SIInstrInfo.h | 818 return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8; in getOpSize()
827 assert(RI.getRegSizeInBits(*RI.getSubClassWithSubReg( in getOpSize()
834 return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8; in getOpSize()
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| D | SIInstrInfo.cpp | 303 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16; in getMemOperandWithOffset()
307 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8; in getMemOperandWithOffset()
491 return (NumLoads * (RI.getRegSizeInBits(*DstRC) / 8)) <= LoadClusterThreshold; in shouldClusterMemOps()
692 if (!(RI.getRegSizeInBits(*RC) % 64)) { in copyPhysReg()
795 if (RI.getRegSizeInBits(*RegClass) > 32) { in materializeImmediate()
977 if (RI.getRegSizeInBits(*DstRC) == 32) { in getMovOpcode()
979 } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) { in getMovOpcode()
981 } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) { in getMovOpcode()
2178 unsigned DstSize = RI.getRegSizeInBits(*DstRC); in insertSelect()
3425 uint32_t DstSize = RI.getRegSizeInBits(*DstRC) / 32; in verifyInstruction()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRAsmPrinter.cpp | 112 unsigned BytesPerReg = TRI.getRegSizeInBits(*RC) / 8; in PrintAsmOperand()
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| D | AVRFrameLowering.cpp | 254 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 && in spillCalleeSavedRegisters()
292 assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 && in restoreCalleeSavedRegisters()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 851 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 && in shouldCoalesce()
852 getRegSizeInBits(*SrcRC) < 256) in shouldCoalesce()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 271 unsigned getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits() function
741 unsigned getRegSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI) const;
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonVExtract.cpp | 161 unsigned VecSize = HRI.getRegSizeInBits(VecRC) / 8; in runOnMachineFunction()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 338 unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8; in printSavedRegsBitmask()
339 unsigned FGR32RegSize = TRI->getRegSizeInBits(Mips::FGR32RegClass) / 8; in printSavedRegsBitmask()
340 unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8; in printSavedRegsBitmask()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfo.cpp | 125 Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ? in storeRegToStackSlot()
152 Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ? in loadRegFromStackSlot()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 137 unsigned RegSize = TRI.getRegSizeInBits(*RC); in addMachineReg()
|