Searched refs:getRegState (Results 1 – 9 of 9) sorted by relevance
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZPostRewrite.cpp | 124 .addReg(MBBI->getOperand(1).getReg(), getRegState(MBBI->getOperand(1))); in selectSELRMux()
131 .addReg(MBBI->getOperand(2).getReg(), getRegState(MBBI->getOperand(2))); in selectSELRMux()
201 .addReg(MI.getOperand(2).getReg(), getRegState(MI.getOperand(2))); in expandCondMove()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonSplitDouble.cpp | 642 unsigned RSA = getRegState(AdrOp); in splitMemRef()
745 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg()); in splitCombine()
753 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine()
768 unsigned RS = getRegState(Op1); in splitExt()
802 unsigned RS = getRegState(Op1); in splitShift()
922 unsigned RS1 = getRegState(Op1); in splitAslOr()
923 unsigned RS2 = getRegState(Op2); in splitAslOr()
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| D | HexagonExpandCondsets.cpp | 639 unsigned PredState = getRegState(PredOp) & ~RegState::Kill; in genCondTfrFor()
643 unsigned SrcState = getRegState(SrcOp); in genCondTfrFor()
696 unsigned S = getRegState(ST); in split()
885 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg()); in predicateAt()
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| D | HexagonInstrInfo.cpp | 1069 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1086 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill) in expandPostRAPseudo()
1091 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1107 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1109 .addReg(SrcOp.getReg(), getRegState(SrcOp)) in expandPostRAPseudo()
1124 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill) in expandPostRAPseudo()
1129 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1263 unsigned PState = getRegState(Op1); in expandPostRAPseudo()
1297 unsigned PState = getRegState(Op1); in expandPostRAPseudo()
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| D | HexagonConstPropagation.cpp | 2995 .addReg(R1.Reg, getRegState(Acc), R1.SubReg); in rewriteHexConstUses()
3025 .addReg(Src1.getReg(), getRegState(Src1), Src1.getSubReg()) in rewriteHexConstUses()
3026 .addReg(OpR2.getReg(), getRegState(OpR2), OpR2.getSubReg()) in rewriteHexConstUses()
3061 .addReg(SR.Reg, getRegState(SO), SR.SubReg); in rewriteHexConstUses()
3093 .addReg(SR.Reg, getRegState(SO), SR.SubReg); in rewriteHexConstUses()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | UnreachableBlockElim.cpp | 198 .addReg(InputReg, getRegState(Input), InputSub); in runOnMachineFunction()
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| D | MachinePipeliner.cpp | 369 .addReg(RegOp.getReg(), getRegState(RegOp), in preprocessPhiNodes()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 496 inline unsigned getRegState(const MachineOperand &RegOp) { in getRegState() function
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 4172 unsigned MaskState = getRegState(MIB->getOperand(1)); in expandPostRAPseudo()
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