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/third_party/mesa3d/src/amd/compiler/
Daco_opcodes.py379 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOP2, InstrClass.Salu):
380 opcode(name, gfx7, gfx9, gfx10, Format.SOP2, cls)
415 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOPK, InstrClass.Salu):
416 opcode(name, gfx7, gfx9, gfx10, Format.SOPK, cls)
493 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOP1, InstrClass.Salu):
494 opcode(name, gfx7, gfx9, gfx10, Format.SOP1, cls)
521 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in SOPC:
522 opcode(name, gfx7, gfx9, gfx10, Format.SOPC, InstrClass.Salu)
568 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, cls) in default_class(SOPP, InstrClass.Salu):
569 opcode(name, gfx7, gfx9, gfx10, Format.SOPP, cls)
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/third_party/mesa3d/src/amd/common/
Dac_surface.c150 return (!surf->u.gfx9.color.dcc.independent_64B_blocks && in ac_surface_supports_dcc_image_stores()
151 surf->u.gfx9.color.dcc.independent_128B_blocks && in ac_surface_supports_dcc_image_stores()
152 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_128B) || in ac_surface_supports_dcc_image_stores()
154 surf->u.gfx9.color.dcc.independent_64B_blocks && in ac_surface_supports_dcc_image_stores()
155 surf->u.gfx9.color.dcc.independent_128B_blocks && in ac_surface_supports_dcc_image_stores()
156 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B); in ac_surface_supports_dcc_image_stores()
185 surf->u.gfx9.color.dcc.independent_64B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier); in ac_modifier_fill_dcc_params()
186 surf->u.gfx9.color.dcc.independent_128B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier); in ac_modifier_fill_dcc_params()
187 …surf->u.gfx9.color.dcc.max_compressed_block_size = AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modif… in ac_modifier_fill_dcc_params()
1446 …return surf->u.gfx9.color.dcc.independent_64B_blocks && !surf->u.gfx9.color.dcc.independent_128B_b… in is_dcc_supported_by_L2()
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Dac_surface_modifier_test.c78 din.swizzleMode = surf->u.gfx9.swizzle_mode; in get_addr_from_coord_base()
86 din.dccKeyFlags.pipeAligned = surf->u.gfx9.color.dcc.pipe_aligned; in get_addr_from_coord_base()
87 din.dccKeyFlags.rbAligned = surf->u.gfx9.color.dcc.rb_aligned; in get_addr_from_coord_base()
95 dcc_input.swizzleMode = surf->u.gfx9.swizzle_mode; in get_addr_from_coord_base()
128 _mesa_sha1_update(&ctx, &surf->u.gfx9.color.display_dcc_pitch_max, in generate_hash()
129 sizeof(surf->u.gfx9.color.display_dcc_pitch_max)); in generate_hash()
133 input.swizzleMode = surf->u.gfx9.swizzle_mode; in generate_hash()
142 input.pitchInElement = surf->u.gfx9.surf_pitch; in generate_hash()
148 surf->u.gfx9.color.dcc.rb_aligned, in generate_hash()
149 surf->u.gfx9.color.dcc.pipe_aligned); in generate_hash()
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Dac_surface_meta_address_test.c266 assert(dout.equation.gfx9.num_bits <= ARRAY_SIZE(eq.u.gfx9.bit)); in one_dcc_address_test()
288 … addr = gfx9_meta_addr_from_coord(info, &dout.equation.gfx9, dout.metaBlkWidth, dout.metaBlkHeight, in one_dcc_address_test()
294 … gfx9_meta_addr_from_coord(info, &dout.equation.gfx9, dout.metaBlkWidth, dout.metaBlkHeight, in one_dcc_address_test()
607 addr = gfx9_meta_addr_from_coord(info, &cout.equation.gfx9, in one_cmask_address_test()
/third_party/mesa3d/src/amd/vulkan/
Dradv_meta_dcc_retile.c62 nir_imm_ivec2(&b, surf->u.gfx9.color.dcc_block_width, surf->u.gfx9.color.dcc_block_height)); in build_dcc_retile_compute_shader()
65 &surf->u.gfx9.color.dcc_equation, src_dcc_pitch, in build_dcc_retile_compute_shader()
69 &b, &dev->physical_device->rad_info, surf->bpe, &surf->u.gfx9.color.display_dcc_equation, in build_dcc_retile_compute_shader()
172 &vk_pipeline_info, NULL, &device->meta_state.dcc_retile.pipeline[surf->u.gfx9.swizzle_mode]); in radv_device_init_meta_dcc_retile_state()
198 unsigned swizzle_mode = image->planes[0].surface.u.gfx9.swizzle_mode; in radv_retile_dcc()
234 .range = image->planes[0].surface.u.gfx9.color.display_dcc_size, in radv_retile_dcc()
265 unsigned dcc_width = DIV_ROUND_UP(width, image->planes[0].surface.u.gfx9.color.dcc_block_width); in radv_retile_dcc()
267 DIV_ROUND_UP(height, image->planes[0].surface.u.gfx9.color.dcc_block_height); in radv_retile_dcc()
270 image->planes[0].surface.u.gfx9.color.dcc_pitch_max + 1, in radv_retile_dcc()
271 image->planes[0].surface.u.gfx9.color.dcc_height, in radv_retile_dcc()
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Dradv_image.c118 return info->bo_metadata->u.gfx9.scanout; in radv_surface_has_scanout()
423 if (md->u.gfx9.swizzle_mode > 0) in radv_patch_surface_from_metadata()
428 surface->u.gfx9.swizzle_mode = md->u.gfx9.swizzle_mode; in radv_patch_surface_from_metadata()
733 va += plane->surface.u.gfx9.zs.stencil_offset; in si_set_mutable_tex_desc_fields()
735 va += plane->surface.u.gfx9.surf_offset; in si_set_mutable_tex_desc_fields()
771 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.zs.stencil_swizzle_mode); in si_set_mutable_tex_desc_fields()
773 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.swizzle_mode); in si_set_mutable_tex_desc_fields()
785 meta = plane->surface.u.gfx9.color.dcc; in si_set_mutable_tex_desc_fields()
800 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.zs.stencil_swizzle_mode); in si_set_mutable_tex_desc_fields()
801 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.zs.stencil_epitch); in si_set_mutable_tex_desc_fields()
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/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_shaderlib_nir.c83 coord = nir_imul(&b, coord, nir_imm_ivec2(&b, surf->u.gfx9.color.dcc_block_width, in si_create_dcc_retile_cs()
84 surf->u.gfx9.color.dcc_block_height)); in si_create_dcc_retile_cs()
87 … ac_nir_dcc_addr_from_coord(&b, &sctx->screen->info, surf->bpe, &surf->u.gfx9.color.dcc_equation, in si_create_dcc_retile_cs()
95 …ac_nir_dcc_addr_from_coord(&b, &sctx->screen->info, surf->bpe, &surf->u.gfx9.color.display_dcc_equ… in si_create_dcc_retile_cs()
129 nir_channels(&b, nir_imm_ivec4(&b, tex->surface.u.gfx9.color.dcc_block_width, in gfx9_create_clear_dcc_msaa_cs()
130 tex->surface.u.gfx9.color.dcc_block_height, in gfx9_create_clear_dcc_msaa_cs()
131 … tex->surface.u.gfx9.color.dcc_block_depth, 0), 0x7)); in gfx9_create_clear_dcc_msaa_cs()
135 &tex->surface.u.gfx9.color.dcc_equation, in gfx9_create_clear_dcc_msaa_cs()
Dsi_sdma_copy_image.c116 uint64_t dst_address = sdst->buffer.gpu_address + sdst->surface.u.gfx9.surf_offset; in si_sdma_v4_v5_copy_texture()
117 uint64_t src_address = ssrc->buffer.gpu_address + ssrc->surface.u.gfx9.surf_offset; in si_sdma_v4_v5_copy_texture()
118 unsigned dst_pitch = sdst->surface.u.gfx9.surf_pitch; in si_sdma_v4_v5_copy_texture()
119 unsigned src_pitch = ssrc->surface.u.gfx9.surf_pitch; in si_sdma_v4_v5_copy_texture()
135 src_address += ssrc->surface.u.gfx9.offset[0]; in si_sdma_v4_v5_copy_texture()
136 dst_address += sdst->surface.u.gfx9.offset[0]; in si_sdma_v4_v5_copy_texture()
159 unsigned linear_slice_pitch = ((uint64_t)linear->surface.u.gfx9.surf_slice_size) / bpp; in si_sdma_v4_v5_copy_texture()
167 linear_address += linear->surface.u.gfx9.offset[0]; in si_sdma_v4_v5_copy_texture()
189 tiled->surface.u.gfx9.swizzle_mode << 3 | in si_sdma_v4_v5_copy_texture()
190 tiled->surface.u.gfx9.resource_type << 9 | in si_sdma_v4_v5_copy_texture()
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Dsi_compute_blit.c481 ssrc->surface.u.gfx9.color.dcc.pipe_aligned); in si_compute_copy_image()
485 sdst->surface.u.gfx9.color.dcc.pipe_aligned); in si_compute_copy_image()
545 info.block[0] = ssrc->surface.u.gfx9.color.dcc_block_width; in si_compute_copy_image()
546 info.block[1] = ssrc->surface.u.gfx9.color.dcc_block_height; in si_compute_copy_image()
547 info.block[2] = ssrc->surface.u.gfx9.color.dcc_block_depth; in si_compute_copy_image()
615 sctx->cs_user_data[1] = (tex->surface.u.gfx9.color.dcc_pitch_max + 1) | in si_retile_dcc()
616 (tex->surface.u.gfx9.color.dcc_height << 16); in si_retile_dcc()
617 sctx->cs_user_data[2] = (tex->surface.u.gfx9.color.display_dcc_pitch_max + 1) | in si_retile_dcc()
618 (tex->surface.u.gfx9.color.display_dcc_height << 16); in si_retile_dcc()
623 void **shader = &sctx->cs_dcc_retile[tex->surface.u.gfx9.swizzle_mode]; in si_retile_dcc()
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Dsi_clear.c312 dcc_offset += tex->surface.u.gfx9.meta_levels[level].offset; in vi_dcc_get_clear_info()
313 clear_size = tex->surface.u.gfx9.meta_levels[level].size; in vi_dcc_get_clear_info()
379 assert(tex->surface.u.gfx9.swizzle_mode >= 4); in si_set_optimal_micro_tile_mode()
389 assert(tex->surface.u.gfx9.swizzle_mode % 4 != 0); in si_set_optimal_micro_tile_mode()
393 tex->surface.u.gfx9.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
394 tex->surface.u.gfx9.swizzle_mode += 2; /* D */ in si_set_optimal_micro_tile_mode()
397 tex->surface.u.gfx9.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
398 tex->surface.u.gfx9.swizzle_mode += 1; /* S */ in si_set_optimal_micro_tile_mode()
401 tex->surface.u.gfx9.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
402 tex->surface.u.gfx9.swizzle_mode += 3; /* R */ in si_set_optimal_micro_tile_mode()
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/third_party/mesa3d/docs/relnotes/
D17.3.3.rst58 - Revert "radv/gfx9: fix block compression texture views."
69 - radv/gfx9: fix 3d image to image transfers on compute queues.
70 - radv/gfx9: fix 3d image clears on compute queues
71 - radv/gfx9: fix buffer to image for 3d images on compute queues
72 - radv/gfx9: fix block compression texture views.
73 - radv/gfx9: use a bigger hammer to flush cb/db caches.
74 - radv/gfx9: use correct swizzle parameter to work out border swizzle.
D17.2.1.rst67 - radv: disable 1d/2d linear optimisation on gfx9.
68 - radv/gfx9: set descriptor up for base_mip to level range.
71 - radv/gfx9: allocate events from uncached VA space
75 - radv/gfx9: set mip0-depth correctly for 2d arrays/3d images
77 - radv/gfx9: fix image resource handling.
84 - cherry-ignore: ignore gfx9 tile swizzle fix
128 - radeonsi/gfx9: always flush DB metadata on framebuffer changes
D17.3.2.rst50 - radv/gfx9: add support for 3d images to blit 2d paths
54 - radv/gfx9: add 3d sampler image->buffer copy shader. (v3)
73 - radv/gfx9: fix primitive topology when adjacency is used
D17.1.10.rst52 - cherry-ignore: add "radv: gfx9 fixes"
53 - cherry-ignore: add "radv/gfx9: set mip0-depth correctly for 2d
55 - cherry-ignore: add "radv/gfx9: fix image resource handling."
100 - cherry-ignore: add "ac/surface: handle S8 on gfx9"
D17.1.6.rst94 - cherry-ignore: add a couple of radeonsi/gfx9 commits
164 - radeonsi/gfx9: fix crash building monolithic merged ES-GS shader
166 - radeonsi/gfx9: reduce max threads per block to 1024 on gfx9+
D17.2.5.rst91 - radeon/video: add gfx9 offsets when rejoin the video surface
97 - ac/surface/gfx9: don't allow DCC for the smallest mipmap levels
109 - amd/common/gfx9: workaround DCC corruption more conservatively
D17.2.2.rst58 - ac/surface: handle S8 on gfx9
63 - radv: add gfx9 scissor workaround
104 - cherry-ignore: add "radeonsi/gfx9: proper workaround for LS/HS VGPR
D17.1.9.rst48 - cherry-ignore: add "radeonsi/gfx9: always flush DB metadata on
52 - cherry-ignore: add "radeonsi/gfx9: proper workaround for LS/HS VGPR
D19.0.4.rst166 - radeonsi/gfx9: set that window_rectangles always roll the context
167 - radeonsi/gfx9: rework the gfx9 scissor bug workaround (v2)
D18.2.7.rst60 - radv: Clamp gfx9 image view extents to the allocated image extents.
67 - radv: use 3d shader for gfx9 copies if dst is 3d
/third_party/mesa3d/src/amd/addrlib/
Dmeson.build38 'src/gfx9/gfx9addrlib.cpp',
39 'src/gfx9/gfx9addrlib.h',
45 'src/chip/gfx9/gfx9_gb_reg.h',
76 'inc', 'src', 'src/core', 'src/chip/gfx9', 'src/chip/r800',
/third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_bo.c916 tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, md->u.gfx9.swizzle_mode); in radv_amdgpu_winsys_bo_set_metadata()
917 tiling_flags |= AMDGPU_TILING_SET(DCC_OFFSET_256B, md->u.gfx9.dcc_offset_256b); in radv_amdgpu_winsys_bo_set_metadata()
918 tiling_flags |= AMDGPU_TILING_SET(DCC_PITCH_MAX, md->u.gfx9.dcc_pitch_max); in radv_amdgpu_winsys_bo_set_metadata()
919 tiling_flags |= AMDGPU_TILING_SET(DCC_INDEPENDENT_64B, md->u.gfx9.dcc_independent_64b_blocks); in radv_amdgpu_winsys_bo_set_metadata()
921 AMDGPU_TILING_SET(DCC_INDEPENDENT_128B, md->u.gfx9.dcc_independent_128b_blocks); in radv_amdgpu_winsys_bo_set_metadata()
923 AMDGPU_TILING_SET(DCC_MAX_COMPRESSED_BLOCK_SIZE, md->u.gfx9.dcc_max_compressed_block_size); in radv_amdgpu_winsys_bo_set_metadata()
924 tiling_flags |= AMDGPU_TILING_SET(SCANOUT, md->u.gfx9.scanout); in radv_amdgpu_winsys_bo_set_metadata()
970 md->u.gfx9.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); in radv_amdgpu_winsys_bo_get_metadata()
971 md->u.gfx9.scanout = AMDGPU_TILING_GET(tiling_flags, SCANOUT); in radv_amdgpu_winsys_bo_get_metadata()
/third_party/mesa3d/src/gallium/drivers/radeon/
Dradeon_vce_52.c198 RVCE_CS(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe); // encRefPicLumaPitch in create()
199 RVCE_CS(enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe); // encRefPicChromaPitch in create()
200 RVCE_CS(align(enc->luma->u.gfx9.surf_height, 16) / 8); // encRefYHeightInQw in create()
274 enc->luma->u.gfx9.surf_offset); // inputPictureLumaAddressHi/Lo in encode()
276 enc->chroma->u.gfx9.surf_offset); // inputPictureChromaAddressHi/Lo in encode()
277 RVCE_CS(align(enc->luma->u.gfx9.surf_height, 16)); // encInputFrameYPitch in encode()
278 RVCE_CS(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe); // encInputPicLumaPitch in encode()
279 RVCE_CS(enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe); // encInputPicChromaPitch in encode()
Dradeon_vce.c226 pitch = align(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe, 256); in si_vce_frame_offset()
227 vpitch = align(enc->luma->u.gfx9.surf_height, 16); in si_vce_frame_offset()
457 align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) * in si_vce_create_encoder()
458 align(tmp_surf->u.gfx9.surf_height, 32); in si_vce_create_encoder()
Dradeon_vcn_dec_jpeg.c47 dec->jpg.dt_luma_top_offset = luma->surface.u.gfx9.surf_offset; in radeon_jpeg_get_decode_param()
49 dec->jpg.dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset; in radeon_jpeg_get_decode_param()
50 dec->jpg.dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w; in radeon_jpeg_get_decode_param()

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