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Searched refs:gpu_address (Results 1 – 25 of 39) sorted by relevance

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/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_cp_reg_shadowing.c34 uint64_t gpu_address = shadow_regs->gpu_address; in si_build_load_reg() local
43 gpu_address += SI_SHADOWED_UCONFIG_REG_OFFSET; in si_build_load_reg()
48 gpu_address += SI_SHADOWED_CONTEXT_REG_OFFSET; in si_build_load_reg()
53 gpu_address += SI_SHADOWED_SH_REG_OFFSET; in si_build_load_reg()
60 si_pm4_cmd_add(pm4, gpu_address); in si_build_load_reg()
61 si_pm4_cmd_add(pm4, gpu_address >> 32); in si_build_load_reg()
Dsi_cp_dma.c194 uint64_t va = (sdst ? sdst->gpu_address : 0) + offset; in si_cp_dma_clear_buffer()
270 va = sctx->scratch_buffer->gpu_address; in si_cp_dma_realign_engine()
302 dst_offset += si_resource(dst)->gpu_address; in si_cp_dma_copy_buffer()
305 src_offset += si_resource(src)->gpu_address; in si_cp_dma_copy_buffer()
395 uint64_t address = si_resource(buf)->gpu_address + offset; in si_cp_dma_prefetch()
491 uint64_t va = buf->gpu_address + offset; in si_cp_write_data()
514 uint64_t dst_va = (dst ? dst->gpu_address : 0ull) + dst_offset; in si_cp_copy_data()
515 uint64_t src_va = (src ? src->gpu_address : 0ull) + src_offset; in si_cp_copy_data()
Dsi_buffer.c182 res->gpu_address = sscreen->ws->buffer_get_virtual_address(res->buf); in si_alloc_resource()
185 uint64_t start = res->gpu_address; in si_alloc_resource()
202 res->gpu_address, res->gpu_address + res->buf->size, res->buf->size); in si_alloc_resource()
286 sdst->gpu_address = ssrc->gpu_address; in si_replace_buffer_storage()
649 buf->gpu_address = ws->buffer_get_virtual_address(buf->buf); in si_buffer_from_user_memory()
667 res->gpu_address = sscreen->ws->buffer_get_virtual_address(res->buf); in si_buffer_from_winsys_buffer()
Dsi_compute.c316 uint64_t base_address = program->shader.bo->gpu_address; in si_bind_compute_state()
359 va = si_resource(resources[i])->gpu_address; in si_set_global_binding()
390 uint64_t bc_va = sctx->border_color_buffer->gpu_address; in si_emit_initial_compute_regs()
411 uint64_t bc_va = sctx->border_color_buffer->gpu_address; in si_emit_initial_compute_regs()
464 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address; in si_setup_compute_scratch_buffer()
530 shader_va = shader->bo->gpu_address + offset; in si_switch_compute_shader()
572 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address; in setup_scratch_rsrc_user_sgprs()
660 dispatch_va = dispatch_buf->gpu_address + dispatch_offset; in si_setup_user_sgprs_co_v2()
706 kernel_args_va = input_buffer->gpu_address + kernel_args_offset; in si_upload_compute_input()
824 uint64_t base_va = si_resource(info->indirect)->gpu_address; in si_emit_dispatch_packets()
Dsi_state_streamout.c240 va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset; in gfx10_emit_streamout_begin()
265 uint64_t va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset; in gfx10_emit_streamout_end()
331 uint64_t va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset; in si_emit_streamout_begin()
380 va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset; in si_emit_streamout_end()
Dsi_fence.c97 radeon_emit(scratch->gpu_address); in si_cp_release_mem()
98 radeon_emit(scratch->gpu_address >> 32); in si_cp_release_mem()
116 uint64_t va = scratch->gpu_address; in si_cp_release_mem()
255 uint64_t fence_va = fine->buf->gpu_address + fine->offset; in si_fine_fence_set()
Dsi_descriptors.c149 desc->gpu_address = si_desc_extract_buffer_address(descriptor); in si_upload_descriptors()
159 desc->gpu_address = 0; in si_upload_descriptors()
171 desc->gpu_address = desc->buffer->gpu_address + buffer_offset; in si_upload_descriptors()
174 assert((desc->buffer->gpu_address >> 32) == sctx->screen->info.address32_hi); in si_upload_descriptors()
175 assert((desc->gpu_address >> 32) == sctx->screen->info.address32_hi); in si_upload_descriptors()
270 uint64_t va = buf->gpu_address + offset; in si_set_buf_desc_address()
300 va = tex->buffer.gpu_address; in si_set_mutable_tex_desc_fields()
323 meta_va = tex->buffer.gpu_address + tex->surface.meta_offset; in si_set_mutable_tex_desc_fields()
335 meta_va = tex->buffer.gpu_address + tex->surface.meta_offset; in si_set_mutable_tex_desc_fields()
1117 assert(va >= res->gpu_address && va + *size <= res->gpu_address + res->bo_size); in si_get_buffer_from_descriptors()
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Dsi_sdma_copy_image.c116 uint64_t dst_address = sdst->buffer.gpu_address + sdst->surface.u.gfx9.surf_offset; in si_sdma_v4_v5_copy_texture()
117 uint64_t src_address = ssrc->buffer.gpu_address + ssrc->surface.u.gfx9.surf_offset; in si_sdma_v4_v5_copy_texture()
229 …uint64_t dst_address = sdst->buffer.gpu_address + sdst->surface.u.legacy.level[0].offset_256B * 25… in cik_sdma_copy_texture()
230 …uint64_t src_address = ssrc->buffer.gpu_address + ssrc->surface.u.legacy.level[0].offset_256B * 25… in cik_sdma_copy_texture()
Dsi_perfcounter.c131 si_cp_copy_data(sctx, &sctx->gfx_cs, COPY_DATA_DST_MEM, buffer, va - buffer->gpu_address, in si_pc_emit_start()
270 uint64_t va = query->buffer.buf->gpu_address + query->buffer.results_end; in si_pc_query_resume()
281 uint64_t va = query->buffer.buf->gpu_address + query->buffer.results_end; in si_pc_query_suspend()
Dsi_texture.c327 tex->cmask_base_address_reg = tex->buffer.gpu_address >> 8; in si_texture_discard_cmask()
456 tex->buffer.gpu_address = new_tex->buffer.gpu_address; in si_reallocate_texture_inplace()
996 resource->gpu_address = plane0->buffer.gpu_address; in si_texture_create_object()
1005 resource->gpu_address = sscreen->ws->buffer_get_virtual_address(resource->buf); in si_texture_create_object()
1108 tex->cmask_base_address_reg = (tex->buffer.gpu_address + tex->surface.cmask_offset) >> 8; in si_texture_create_object()
1114 tex->buffer.gpu_address, tex->buffer.gpu_address + tex->buffer.buf->size, in si_texture_create_object()
1728 tex->cmask_base_address_reg = (tex->buffer.gpu_address + tex->surface.cmask_offset) >> 8; in si_texture_invalidate_storage()
Dgfx10_query.c176 uint64_t fence_va = query->last->buf->gpu_address; in gfx10_sh_query_end()
398 va = qbuf->buf->gpu_address; in gfx10_sh_query_get_result_resource()
Dsi_query.c830 va = query->buffer.buf->gpu_address + query->buffer.results_end; in si_query_hw_emit_start()
918 va = query->buffer.buf->gpu_address + query->buffer.results_end; in si_query_hw_emit_stop()
992 uint64_t va_base = qbuf->buf->gpu_address; in si_emit_query_predication()
1052 uint64_t va = query->workaround_buf->gpu_address + query->workaround_offset; in si_emit_query_predication()
1062 uint64_t va_base = qbuf->buf->gpu_address; in si_emit_query_predication()
1551 va = qbuf->buf->gpu_address + qbuf->results_end - query->result_size; in si_query_hw_get_result_resource()
Dsi_state_draw.cpp295 shader->bo->gpu_address); in si_update_shaders()
679 si_resource(sctx->tess_rings_tmz) : si_resource(sctx->tess_rings))->gpu_address; in si_emit_derived_tess_state()
1387 index_va = si_resource(indexbuf)->gpu_address + index_offset; in si_emit_draw_packets()
1404 uint64_t indirect_va = si_resource(indirect->buffer)->gpu_address; in si_emit_draw_packets()
1447 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset; in si_emit_draw_packets()
1674 uint64_t va = buf->gpu_address + offset; in si_set_vb_descriptor()
1888 sctx->vb_descriptors_buffer->gpu_address + in si_upload_and_prefetch_VB_descriptors()
Dsi_build_pm4.h279 radeon_emit_32bit_pointer(sctx->screen, (desc)->gpu_address); \
Dsi_state_shaders.c539 va = shader->bo->gpu_address; in si_shader_ls()
560 va = shader->bo->gpu_address; in si_shader_hs()
641 va = shader->bo->gpu_address; in si_shader_es()
885 va = shader->bo->gpu_address; in si_shader_gs()
1172 va = shader->bo->gpu_address; in gfx10_shader_ngg()
1456 va = shader->bo->gpu_address; in si_shader_vs()
1728 va = shader->bo->gpu_address; in si_shader_ps()
3729 uint64_t scratch_va = sctx->scratch_buffer->gpu_address; in si_update_scratch_buffer()
3912 si_resource(sctx->tess_rings)->gpu_address + sctx->screen->tess_offchip_ring_size; in si_init_tess_factor_ring()
3972 si_resource(sctx->tess_rings_tmz)->gpu_address + sctx->screen->tess_offchip_ring_size; in si_init_tess_factor_ring()
Dsi_state.c2563 surf->db_depth_base = tex->buffer.gpu_address >> 8; in si_init_depth_surface()
2564 … surf->db_stencil_base = (tex->buffer.gpu_address + tex->surface.u.gfx9.zs.stencil_offset) >> 8; in si_init_depth_surface()
2591 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8; in si_init_depth_surface()
2605 (tex->buffer.gpu_address >> 8) + tex->surface.u.legacy.level[level].offset_256B; in si_init_depth_surface()
2607 (tex->buffer.gpu_address >> 8) + tex->surface.u.legacy.zs.stencil_level[level].offset_256B; in si_init_depth_surface()
2663 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8; in si_init_depth_surface()
3076 cb_color_base = tex->buffer.gpu_address >> 8; in si_emit_framebuffer_state()
3101 cb_color_fmask = (tex->buffer.gpu_address + tex->surface.fmask_offset) >> 8; in si_emit_framebuffer_state()
3114 cb_dcc_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8; in si_emit_framebuffer_state()
3904 va = tex->buffer.gpu_address + tex->surface.fmask_offset; in gfx10_make_texture_descriptor()
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/third_party/mesa3d/src/gallium/drivers/r600/
Dr600_buffer_common.c209 res->gpu_address = rscreen->ws->buffer_get_virtual_address(res->buf); in r600_alloc_resource()
211 res->gpu_address = 0; in r600_alloc_resource()
220 res->gpu_address, res->gpu_address + res->buf->size, in r600_alloc_resource()
274 uint64_t old_gpu_address = rdst->gpu_address; in r600_replace_buffer_storage()
277 rdst->gpu_address = rsrc->gpu_address; in r600_replace_buffer_storage()
660 rbuffer->gpu_address = in r600_buffer_from_user_memory()
663 rbuffer->gpu_address = 0; in r600_buffer_from_user_memory()
Devergreen_hw_context.c49 dst_offset += rdst->gpu_address; in evergreen_dma_copy_buffer()
50 src_offset += rsrc->gpu_address; in evergreen_dma_copy_buffer()
99 offset += r600_resource(dst)->gpu_address; in evergreen_cp_dma_clear_buffer()
Dr600_streamout.c196 uint64_t va = r600_resource(t[i]->b.buffer)->gpu_address; in r600_emit_streamout_begin()
221 uint64_t va = t[i]->buf_filled_size->gpu_address + in r600_emit_streamout_begin()
267 va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset; in r600_emit_streamout_end()
Devergreen_state.c661 va = tmp->resource.gpu_address + params->offset; in evergreen_fill_buffer_resource_words()
706 if (tmp->resource.gpu_address) in texture_buffer_sampler_view()
831 va = tmp->resource.gpu_address; in evergreen_fill_tex_resource_words()
1110 color->offset = (res->gpu_address + first_element) >> 8; in evergreen_set_color_surface_buffer()
1136 color->offset += rtex->resource.gpu_address; in evergreen_set_color_surface_common()
1281 color->fmask = (rtex->resource.gpu_address + rtex->fmask.offset) >> 8; in evergreen_set_color_surface_common()
1368 offset = rtex->resource.gpu_address; in evergreen_init_depth_surface()
1420 stencil_offset += rtex->resource.gpu_address; in evergreen_init_depth_surface()
1435 uint64_t va = rtex->resource.gpu_address + rtex->htile_offset; in evergreen_init_depth_surface()
1780 …set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_address >> 8); in evergreen_emit_image_state()
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Dr600_hw_context.c466 va = buf->gpu_address + offset; in r600_emit_pfp_sync_me()
516 dst_offset += r600_resource(dst)->gpu_address; in r600_cp_dma_copy_buffer()
517 src_offset += r600_resource(src)->gpu_address; in r600_cp_dma_copy_buffer()
Dr600_texture.c342 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8; in r600_texture_discard_cmask()
409 rtex->resource.gpu_address = new_tex->resource.gpu_address; in r600_reallocate_texture_inplace()
734 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8; in r600_texture_alloc_cmask_separate()
978 resource->gpu_address = rscreen->ws->buffer_get_virtual_address(resource->buf); in r600_texture_create_object()
1005 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8; in r600_texture_create_object()
1009 rtex->resource.gpu_address, in r600_texture_create_object()
1010 rtex->resource.gpu_address + rtex->resource.buf->size, in r600_texture_create_object()
1280 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8; in r600_texture_invalidate_storage()
Dr600_uvd.c128 resources[i]->resource.gpu_address = ctx->b.ws->buffer_get_virtual_address( in r600_video_buffer_create()
Dr600_query.c799 va = query->buffer.buf->gpu_address + query->buffer.results_end; in r600_query_hw_emit_start()
886 va = query->buffer.buf->gpu_address + query->buffer.results_end; in r600_query_hw_emit_stop()
954 uint64_t va_base = qbuf->buf->gpu_address; in r600_emit_query_predication()
1738 va = qbuf->buf->gpu_address + qbuf->results_end - query->result_size; in r600_query_hw_get_result_resource()
1903 radeon_emit(cs, buffer->gpu_address); in r600_query_fix_enabled_rb_mask()
1904 radeon_emit(cs, buffer->gpu_address >> 32); in r600_query_fix_enabled_rb_mask()
/third_party/mesa3d/src/amd/vulkan/
Dradv_image.c670 uint64_t gpu_address = radv_buffer_get_va(buffer->bo); in radv_make_buffer_descriptor() local
671 uint64_t va = gpu_address + buffer->offset; in radv_make_buffer_descriptor()
727 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0; in si_set_mutable_tex_desc_fields() local
728 uint64_t va = gpu_address; in si_set_mutable_tex_desc_fields()
749 meta_va = gpu_address + plane->surface.meta_offset; in si_set_mutable_tex_desc_fields()
757 meta_va = gpu_address + plane->surface.meta_offset; in si_set_mutable_tex_desc_fields()
972 uint64_t gpu_address = radv_buffer_get_va(image->bo); in gfx10_make_texture_descriptor() local
978 va = gpu_address + image->offset + image->planes[0].surface.fmask_offset; in gfx10_make_texture_descriptor()
1011 va = gpu_address + image->offset + image->planes[0].surface.cmask_offset; in gfx10_make_texture_descriptor()
1127 uint64_t gpu_address = radv_buffer_get_va(image->bo); in si_make_texture_descriptor() local
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