| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_shader_args.c | 688 ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[0]); in radv_declare_shader_args()
689 ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[1]); in radv_declare_shader_args()
692 ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[2]); in radv_declare_shader_args()
711 ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[0]); in radv_declare_shader_args()
712 ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[1]); in radv_declare_shader_args()
714 ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[2]); in radv_declare_shader_args()
715 ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[3]); in radv_declare_shader_args()
716 ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[4]); in radv_declare_shader_args()
717 ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.gs_vtx_offset[5]); in radv_declare_shader_args()
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| D | radv_nir_to_llvm.c | 62 LLVMValueRef gs_vtx_offset[6]; member
1580 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.gs_vtx_offset[0]), 0, 16), in handle_ngg_outputs_post_2()
1581 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.gs_vtx_offset[0]), 16, 16), in handle_ngg_outputs_post_2()
1582 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.gs_vtx_offset[1]), 0, 16), in handle_ngg_outputs_post_2()
1645 prim.passthrough = ac_get_arg(&ctx->ac, ctx->args->ac.gs_vtx_offset[0]); in handle_ngg_outputs_post_2()
2354 ctx->gs_vtx_offset[i] = ac_unpack_param( in prepare_gs_input_vgprs()
2355 &ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.gs_vtx_offset[i / 2]), (i & 1) * 16, 16); in prepare_gs_input_vgprs()
2362 ctx->gs_vtx_offset[i] = ac_get_arg(&ctx->ac, ctx->args->ac.gs_vtx_offset[i]); in prepare_gs_input_vgprs()
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_shader_llvm_gs.c | 61 si_unpack_param(ctx, ctx->args.gs_vtx_offset[index / 2], (index & 1) * 16, 16); in si_llvm_load_input_gs()
74 LLVMValueRef gs_vtx_offset = ac_get_arg(&ctx->ac, ctx->args.gs_vtx_offset[vtx_offset_param]); in si_llvm_load_input_gs() local
76 vtx_offset = LLVMBuildMul(ctx->ac.builder, gs_vtx_offset, LLVMConstInt(ctx->ac.i32, 4, 0), ""); in si_llvm_load_input_gs()
127 ret = si_insert_input_ret_float(ctx, ret, ctx->args.gs_vtx_offset[0], vgpr++); in si_set_es_return_value_for_gs()
128 ret = si_insert_input_ret_float(ctx, ret, ctx->args.gs_vtx_offset[1], vgpr++); in si_set_es_return_value_for_gs()
131 ret = si_insert_input_ret_float(ctx, ret, ctx->args.gs_vtx_offset[2], vgpr++); in si_set_es_return_value_for_gs()
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| D | si_shader.c | 550 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_vtx_offset[0]); in si_init_shader_args()
551 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_vtx_offset[1]); in si_init_shader_args()
554 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_vtx_offset[2]); in si_init_shader_args()
625 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_vtx_offset[0]); in si_init_shader_args()
626 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_vtx_offset[1]); in si_init_shader_args()
628 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_vtx_offset[2]); in si_init_shader_args()
629 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_vtx_offset[3]); in si_init_shader_args()
630 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_vtx_offset[4]); in si_init_shader_args()
631 ac_add_arg(&ctx->args, AC_ARG_VGPR, 1, AC_ARG_INT, &ctx->args.gs_vtx_offset[5]); in si_init_shader_args()
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| D | gfx10_shader_ngg.c | 148 prim.passthrough = ac_get_arg(&ctx->ac, ctx->args.gs_vtx_offset[0]); in gfx10_ngg_build_export_prim()
192 prim.index[i] = si_unpack_param(ctx, ctx->args.gs_vtx_offset[i / 2], (i & 1) * 16, 16); in gfx10_ngg_build_export_prim()
913 vtxindex[i] = si_unpack_param(ctx, ctx->args.gs_vtx_offset[i / 2], (i & 1) * 16, 16); in gfx10_emit_ngg_culling_epilogue()
1352 vtxindex[i] = si_unpack_param(ctx, ctx->args.gs_vtx_offset[0], 10 * i, 9); in gfx10_emit_ngg_epilogue()
1355 vtxindex[i] = si_unpack_param(ctx, ctx->args.gs_vtx_offset[i / 2], (i & 1) * 16, 16); in gfx10_emit_ngg_epilogue()
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| /third_party/mesa3d/src/amd/common/ |
| D | ac_shader_args.h | 110 struct ac_arg gs_vtx_offset[6]; /* GFX6-8: [0-5], GFX9+: [0-2] packed */ member
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| /third_party/mesa3d/src/amd/llvm/ |
| D | ac_nir_to_llvm.c | 4022 result = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[nir_intrinsic_base(instr)]); in visit_intrinsic()
4222 result = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]); in visit_intrinsic()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 21.3.0.rst | 4132 - radv, ac, aco: Use indices 0-2 of gs_vtx_offset argument array on GFX9+.
4133 - radeonsi: Change GS vertex offset arguments to use gs_vtx_offset array.
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| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_instruction_selection.cpp | 8863 get_arg(ctx, ctx->args->ac.gs_vtx_offset[b])); in visit_intrinsic()
8899 get_arg(ctx, ctx->args->ac.gs_vtx_offset[0])); in visit_intrinsic()
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