Searched refs:has16BitInsts (Results 1 – 8 of 8) sorted by relevance
372 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()387 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()398 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()410 if (ST->has16BitInsts() && SLT == MVT::f16) in getArithmeticInstrCost()432 (SLT == MVT::f16 && ST->has16BitInsts())) { in getArithmeticInstrCost()437 if (SLT == MVT::f16 && ST->has16BitInsts()) { in getArithmeticInstrCost()489 if (ST->has16BitInsts() && SLT == MVT::f16) in getIntrinsicInstrCost()559 if (EltSize == 16 && Index == 0 && ST->has16BitInsts()) in getVectorInstrCost()
264 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()350 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()369 } else if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()384 .clampScalar(0, ST.has16BitInsts() ? S16 : S32, S64); in AMDGPULegalizerInfo()388 .clampScalar(0, ST.has16BitInsts() ? S16 : S32, S64); in AMDGPULegalizerInfo()392 .clampScalar(0, ST.has16BitInsts() ? S16 : S32, S64); in AMDGPULegalizerInfo()403 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()460 if (ST.has16BitInsts()) in AMDGPULegalizerInfo()467 if (ST.has16BitInsts()) in AMDGPULegalizerInfo()479 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()[all …]
468 if (Size <= 16 && ST->has16BitInsts()) in replaceMulWithMul24()887 if (ST->has16BitInsts() && needsPromotionToI32(I.getType()) && in visitBinaryOperator()982 if (ST->has16BitInsts() && needsPromotionToI32(I.getOperand(0)->getType()) && in visitICmpInst()992 if (ST->has16BitInsts() && needsPromotionToI32(I.getType()) && in visitSelectInst()1011 if (ST->has16BitInsts() && needsPromotionToI32(I.getType()) && in visitBitreverseIntrinsicInst()
626 (ScalarVT == MVT::f16 && Subtarget->has16BitInsts())); in isFPImmLegal()745 (Subtarget->has16BitInsts() && VT == MVT::f16); in isFAbsFree()751 (Subtarget->has16BitInsts() && VT == MVT::f16) || in isFNegFree()788 if (DestSize== 16 && Subtarget->has16BitInsts()) in isTruncateFree()798 if (SrcSize == 16 && Subtarget->has16BitInsts()) in isZExtFree()2523 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) { in LowerUINT_TO_FP()2562 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) { in LowerSINT_TO_FP()2716 if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) { in LowerFP_TO_SINT()2739 if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) { in LowerFP_TO_UINT()3315 if (Subtarget->has16BitInsts() && VT.getScalarType().bitsLE(MVT::i16)) in performMulCombine()[all …]
143 bool has16BitInsts() const { in has16BitInsts() function
150 if (Subtarget->has16BitInsts()) { in SITargetLowering()372 if (Subtarget->has16BitInsts()) { in SITargetLowering()446 if (Subtarget->has16BitInsts()) { in SITargetLowering()671 if (Subtarget->has16BitInsts()) { in SITargetLowering()810 if (Size == 16 && Subtarget->has16BitInsts()) in getRegisterTypeForCallingConv()835 if (Size == 16 && Subtarget->has16BitInsts()) in getNumRegistersForCallingConv()868 if (Size == 16 && Subtarget->has16BitInsts()) { in getVectorTypeBreakdownForCallingConv()1384 if (Subtarget->has16BitInsts() && VT == MVT::i16) { in isTypeDesirableForOp()3941 return Subtarget->has16BitInsts() && hasFP64FP16Denormals(MF); in isFMAFasterThanFMulAndFAdd()8646 if (!Subtarget->has16BitInsts() || in performZeroExtendCombine()[all …]
1072 def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
2831 return ST.has16BitInsts() && in isInlineConstant()2880 return ST.has16BitInsts() && in isInlineConstant()