Searched refs:hasAGPRs (Results 1 – 6 of 6) sorted by relevance
130 return !hasVGPRs(RC) && !hasAGPRs(RC); in isSGPRClass()149 return hasAGPRs(RC) && !hasVGPRs(RC); in isAGPRClass()156 bool hasAGPRs(const TargetRegisterClass *RC) const;160 return hasVGPRs(RC) || hasAGPRs(RC); in hasVectorRegisters()
286 bool IsAGPR = TRI->hasAGPRs(DstRC); in foldVGPRCopyIntoRegSequence()805 if (AllAGPRUses && numVGPRUses && !TRI->hasAGPRs(RC0)) { in processPHINode()
647 hasAGPRs(RC) ? TII->getNamedOperand(*MI, AMDGPU::OpName::tmp)->getReg() in buildSpillLoadStore()1300 bool SIRegisterInfo::hasAGPRs(const TargetRegisterClass *RC) const { in hasAGPRs() function in SIRegisterInfo1420 } else if (hasAGPRs(RC)) { in getSubRegClass()1698 return hasAGPRs(RC); in isAGPR()
704 } else if (RI.hasAGPRs(RC)) { in copyPhysReg()707 } else if (RI.hasVGPRs(RC) && RI.hasAGPRs(RI.getPhysRegClass(SrcReg))) { in copyPhysReg()975 if (RI.hasAGPRs(DstRC)) in getMovOpcode()1099 unsigned Opcode = RI.hasAGPRs(RC) ? getAGPRSpillSaveOpcode(SpillSize) in storeRegToStackSlot()1104 if (RI.hasAGPRs(RC)) { in storeRegToStackSlot()1221 unsigned Opcode = RI.hasAGPRs(RC) ? getAGPRSpillRestoreOpcode(SpillSize) in loadRegFromStackSlot()1224 if (RI.hasAGPRs(RC)) { in loadRegFromStackSlot()4195 if (RI.hasAGPRs(MRI.getRegClass(MO.getReg())) && in legalizeOperandsVOP3()4227 if (RI.hasAGPRs(VRC)) { in readlaneVGPRToSGPR()4572 VRC = RI.hasAGPRs(getOpRegClass(MI, 0)) in legalizeOperands()[all …]
92 STI->hasAGPRs(RC) ? in getRegKind()
369 if (TRI->hasAGPRs(TRI->getRegClassForReg(*MRI, R))) in analyzeInst()