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Searched refs:hasInterval (Results 1 – 19 of 19) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DLiveIntervals.h115 if (hasInterval(Reg)) in getInterval()
125 bool hasInterval(Register Reg) const { in hasInterval() function
132 assert(!hasInterval(Reg) && "Interval already exists!"); in createEmptyInterval()
DLiveStacks.h78 bool hasInterval(int Slot) const { return S2IMap.count(Slot); } in hasInterval() function
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DRegAllocBase.cpp145 assert(LIS->hasInterval(Reg)); in allocatePhysRegs()
DLiveDebugVariables.cpp635 if (!LIS->hasInterval(Reg)) { in handleDebugValue()
811 if (!LIS.hasInterval(DstReg)) in addDefsFromCopies()
875 if (LIS.hasInterval(LocMO.getReg())) { in computeIntervals()
DRenameIndependentSubregs.cpp395 if (!LIS->hasInterval(Reg)) in runOnMachineFunction()
DLiveRangeEdit.cpp385 if (LIS.hasInterval(Reg) && MRI.reg_nodbg_empty(Reg)) { in eliminateDeadDef()
DStackSlotColoring.cpp173 if (!LS->hasInterval(FI)) in ScanForSpillSlotRefs()
DMachineVerifier.cpp1824 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) && in visitMachineOperand()
1965 if (LiveInts->hasInterval(Reg)) { in checkLiveness()
2068 if (LiveInts->hasInterval(Reg)) { in checkLiveness()
2368 if (!LiveInts->hasInterval(Reg)) { in verifyLiveIntervals()
DLiveIntervals.cpp165 if (hasInterval(Reg)) in print()
1615 !hasInterval(MOI->getReg())) { in repairIntervalsInRange()
DMachineBasicBlock.cpp1049 if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg)) in SplitCriticalEdge()
DInlineSpiller.cpp701 assert(LIS.hasInterval(Reg) && in reMaterializeAll()
DModuloSchedule.cpp346 if (!LIS.hasInterval(ToReg)) in replaceRegUsesAfterLoop()
DRegAllocGreedy.cpp1512 if (!LIS->hasInterval(Evictor)) in splitCanCauseEvictionChain()
DRegisterCoalescer.cpp3657 if (!LIS->hasInterval(reg)) in lateLiveIntervalUpdate()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DGCNRegPressure.cpp44 if (!LIS.hasInterval(Reg)) in printLivesAt()
281 if (!LIS.hasInterval(Reg)) in getLiveRegs()
DGCNRegPressure.h218 if (!LIS.hasInterval(Reg)) in getLiveRegMap()
DGCNNSAReassign.cpp211 if (!LIS->hasInterval(Reg)) in CheckNSA()
DGCNRegBankReassign.cpp621 if (!LIS->hasInterval(C.Reg)) in tryReassign()
DSIRegisterInfo.cpp1854 if (!LIS->hasInterval(Reg)) in findReachingDef()