| /third_party/mesa3d/src/gallium/drivers/virgl/ |
| D | virgl_staging_mgr.c | 42 vws->resource_reference(vws, &staging->hw_res, NULL); in virgl_staging_alloc_buffer()
48 staging->hw_res = vws->resource_create(vws, in virgl_staging_alloc_buffer()
60 if (staging->hw_res == NULL) in virgl_staging_alloc_buffer()
63 staging->map = vws->resource_map(vws, staging->hw_res); in virgl_staging_alloc_buffer()
65 vws->resource_reference(vws, &staging->hw_res, NULL); in virgl_staging_alloc_buffer()
89 vws->resource_reference(vws, &staging->hw_res, NULL); in virgl_staging_destroy()
123 assert(staging->hw_res); in virgl_staging_alloc()
130 vws->resource_reference(vws, outbuf, staging->hw_res); in virgl_staging_alloc()
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| D | virgl_resource.c | 66 if (!vws->res_is_referenced(vws, vctx->cbuf, res->hw_res)) in virgl_res_needs_flush()
171 wait = (flush || vws->resource_is_busy(vws, res->hw_res)); in virgl_resource_transfer_prepare()
215 (readback || (wait && vws->resource_is_busy(vws, res->hw_res)))) in virgl_resource_transfer_prepare()
219 vws->transfer_get(vws, res->hw_res, &xfer->base.box, xfer->base.stride, in virgl_resource_transfer_prepare()
224 vws->resource_wait(vws, res->hw_res); in virgl_resource_transfer_prepare()
339 struct virgl_hw_res *hw_res; in virgl_resource_realloc() local
343 hw_res = vs->vws->resource_create(vs->vws, in virgl_resource_realloc()
355 if (!hw_res) in virgl_resource_realloc()
358 vs->vws->resource_reference(vs->vws, &res->hw_res, NULL); in virgl_resource_realloc()
359 res->hw_res = hw_res; in virgl_resource_realloc()
[all …]
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| D | virgl_transfer_queue.c | 106 const struct virgl_hw_res *hw_res, in transfer_overlap() argument
113 if (xfer->hw_res != hw_res || xfer->base.level != level) in transfer_overlap()
141 const struct virgl_hw_res *hw_res, in virgl_transfer_queue_find_overlap() argument
148 if (transfer_overlap(xfer, hw_res, level, box, include_touching)) in virgl_transfer_queue_find_overlap()
158 return transfer_overlap(queued, current->hw_res, current->base.level, in transfers_intersect()
187 queue->vs->vws->transfer_put(queue->vs->vws, queued->hw_res, in transfer_put()
352 transfer->hw_res, in virgl_transfer_queue_is_queued()
360 const struct virgl_hw_res *hw_res, in virgl_transfer_queue_extend_buffer() argument
368 queued = virgl_transfer_queue_find_overlap(queue, hw_res, 0, &box, true); in virgl_transfer_queue_extend_buffer()
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| D | virgl_query.c | 158 host_state = vs->vws->resource_map(vs->vws, query->buf->hw_res); in virgl_end_query()
169 vs->vws->emit_res(vs->vws, vctx->cbuf, query->buf->hw_res, false); in virgl_end_query()
187 if (vs->vws->res_is_referenced(vs->vws, vctx->cbuf, query->buf->hw_res)) in virgl_get_query_result()
191 vs->vws->resource_wait(vs->vws, query->buf->hw_res); in virgl_get_query_result()
192 else if (vs->vws->resource_is_busy(vs->vws, query->buf->hw_res)) in virgl_get_query_result()
195 host_state = vs->vws->resource_map(vs->vws, query->buf->hw_res); in virgl_get_query_result()
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| D | virgl_resource.h | 56 struct virgl_hw_res *hw_res; member
80 struct virgl_hw_res *hw_res; member
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| D | virgl_staging_mgr.h | 41 struct virgl_hw_res *hw_res; /* Staging buffer hw_res. */ member
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| D | virgl_transfer_queue.h | 62 const struct virgl_hw_res *hw_res,
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| D | virgl_context.c | 185 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE); in virgl_attach_res_framebuffer()
194 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE); in virgl_attach_res_framebuffer()
214 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE); in virgl_attach_res_sampler_views()
227 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE); in virgl_attach_res_vertex_buffers()
239 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE); in virgl_attach_res_index_buffer()
251 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE); in virgl_attach_res_so_targets()
268 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE); in virgl_attach_res_uniform_buffers()
285 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE); in virgl_attach_res_shader_buffers()
302 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE); in virgl_attach_res_shader_images()
316 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE); in virgl_attach_res_atomic_buffers()
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| D | virgl_texture.c | 184 ptr = vws->resource_map(vws, vtex->hw_res); in texture_transfer_map_resolve()
252 vws->transfer_put(vws, trans->hw_res, box, in flush_data()
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| D | virgl_streamout.c | 86 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE); in virgl_set_so_targets()
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| D | virgl_encode.c | 318 if (res && res->hw_res) in virgl_encoder_emit_resource()
319 vws->emit_res(vws, buf, res->hw_res, TRUE); in virgl_encoder_emit_resource()
867 vs->vws->emit_res(vs->vws, buf, xfer->hw_res, TRUE); in virgl_encoder_transfer3d_common()
893 transfer.hw_res = res->hw_res; in virgl_encoder_inline_write()
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| D | virgl_screen.c | 789 vws->flush_frontbuffer(vws, vres->hw_res, level, layer, winsys_drawable_handle, in virgl_flush_frontbuffer()
889 vscreen->vws->resource_wait(vscreen->vws, res->hw_res); in virgl_query_memory_info()
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| /third_party/mesa3d/src/gallium/drivers/virgl/tests/ |
| D | virgl_staging_mgr_test.cpp | 52 struct virgl_hw_res *hw_res = CALLOC_STRUCT(virgl_hw_res); in fake_resource_create() local
54 pipe_reference_init(&hw_res->reference, 1); in fake_resource_create()
56 hw_res->target = target; in fake_resource_create()
57 hw_res->bind = bind; in fake_resource_create()
58 hw_res->size = size; in fake_resource_create()
59 hw_res->data = CALLOC(size, 1); in fake_resource_create()
61 return hw_res; in fake_resource_create()
80 fake_resource_map(struct virgl_winsys *vws, struct virgl_hw_res *hw_res) in fake_resource_map() argument
82 return hw_res->data; in fake_resource_map()
114 resource_map(struct virgl_hw_res *hw_res) in resource_map() argument
[all …]
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| /third_party/mesa3d/src/gallium/winsys/virgl/drm/ |
| D | virgl_drm_winsys.h | 108 struct virgl_hw_res *hw_res; member
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| D | virgl_drm_winsys.c | 924 fence->hw_res = virgl_drm_winsys_resource_create(vws, PIPE_BUFFER, in virgl_drm_fence_create_legacy()
926 if (!fence->hw_res) { in virgl_drm_fence_create_legacy()
1055 return !virgl_drm_resource_is_busy(vws, fence->hw_res); in virgl_fence_wait()
1060 while (virgl_drm_resource_is_busy(vws, fence->hw_res)) { in virgl_fence_wait()
1067 virgl_drm_resource_wait(vws, fence->hw_res); in virgl_fence_wait()
1083 virgl_drm_resource_reference(vws, &dfence->hw_res, NULL); in virgl_fence_reference()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 21.1.2.rst | 176 - virgl:Fix the leak of hw_res used as fence
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| D | 21.2.0.rst | 5268 - virgl:Fix the leak of hw_res used as fence
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