| /third_party/mesa3d/src/mesa/state_tracker/ |
| D | st_cb_compute.c | 42 GLintptr indirect_offset) in st_dispatch_compute_common() argument
68 info.indirect_offset = indirect_offset; in st_dispatch_compute_common()
81 GLintptr indirect_offset) in st_dispatch_compute_indirect() argument
86 st_dispatch_compute_common(ctx, NULL, NULL, indirect, indirect_offset); in st_dispatch_compute_indirect()
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| D | st_draw.c | 226 GLsizeiptr indirect_offset, in st_indirect_draw_vbo() argument
263 indirect.offset = indirect_offset; in st_indirect_draw_vbo()
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| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_vec4_tcs.cpp | 160 const src_reg &indirect_offset) in emit_input_urb_read() argument
169 indirect_offset); in emit_input_urb_read()
182 if (inst->offset == 0 && indirect_offset.file == BAD_FILE) { in emit_input_urb_read()
195 const src_reg &indirect_offset) in emit_output_urb_read() argument
202 brw_imm_ud(dst.writemask << first_component), indirect_offset); in emit_output_urb_read()
222 const src_reg &indirect_offset) in emit_urb_write() argument
231 brw_imm_ud(writemask), indirect_offset); in emit_urb_write()
261 src_reg indirect_offset = get_indirect_offset(instr); in nir_emit_intrinsic() local
271 first_component, indirect_offset); in nir_emit_intrinsic()
279 src_reg indirect_offset = get_indirect_offset(instr); in nir_emit_intrinsic() local
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| D | brw_vec4_tcs.h | 62 const src_reg &indirect_offset);
66 const src_reg &indirect_offset);
69 unsigned base_offset, const src_reg &indirect_offset);
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| D | brw_vec4_tes.cpp | 161 src_reg indirect_offset = get_indirect_offset(instr); in nir_emit_intrinsic() local
166 if (indirect_offset.file != BAD_FILE) { in nir_emit_intrinsic()
174 retype(indirect_offset, BRW_REGISTER_TYPE_UD), in nir_emit_intrinsic()
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| D | brw_reg.h | 235 int indirect_offset:10; /* relative addressing offset */ member
434 reg.indirect_offset = 0; in brw_reg()
1144 reg.indirect_offset = offset; in brw_vec4_indirect()
1154 reg.indirect_offset = offset; in brw_vec1_indirect()
1165 reg.indirect_offset = offset; in brw_VxH_indirect()
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| D | brw_ir.h | 77 using brw_reg::indirect_offset;
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| D | brw_fs_nir.cpp | 2605 fs_reg indirect_offset = get_nir_src(offset_src); in emit_gs_input_load() local
2628 const fs_reg srcs[] = { icp_handle, indirect_offset }; in emit_gs_input_load()
2897 fs_reg indirect_offset = get_indirect_offset(instr); in nir_emit_tcs_intrinsic() local
2912 if (indirect_offset.file == BAD_FILE) { in nir_emit_tcs_intrinsic()
2929 const fs_reg srcs[] = { icp_handle, indirect_offset }; in nir_emit_tcs_intrinsic()
2955 if (inst->offset == 0 && indirect_offset.file == BAD_FILE) { in nir_emit_tcs_intrinsic()
2967 fs_reg indirect_offset = get_indirect_offset(instr); in nir_emit_tcs_intrinsic() local
2974 if (indirect_offset.file == BAD_FILE) { in nir_emit_tcs_intrinsic()
3003 const fs_reg srcs[] = { output_handles, indirect_offset }; in nir_emit_tcs_intrinsic()
3032 fs_reg indirect_offset = get_indirect_offset(instr); in nir_emit_tcs_intrinsic() local
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| /third_party/mesa3d/src/mesa/drivers/dri/i965/ |
| D | brw_primitive_restart.c | 170 GLsizeiptr indirect_offset, in vbo_sw_primitive_restart_common_start() argument
203 indirect_offset); in vbo_sw_primitive_restart_common_start()
283 GLsizeiptr indirect_offset, in vbo_sw_primitive_restart() argument
295 indirect, indirect_offset, in vbo_sw_primitive_restart()
301 indirect, indirect_offset, in vbo_sw_primitive_restart()
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| D | brw_draw.c | 167 GLsizeiptr indirect_offset) in brw_emit_prim() argument
233 indirect_offset, 5 * sizeof(GLuint), false); in brw_emit_prim()
238 indirect_offset + 0); in brw_emit_prim()
240 indirect_offset + 4); in brw_emit_prim()
243 indirect_offset + 8); in brw_emit_prim()
246 indirect_offset + 12); in brw_emit_prim()
248 indirect_offset + 16); in brw_emit_prim()
251 indirect_offset + 12); in brw_emit_prim()
991 GLsizeiptr indirect_offset) in brw_draw_single_prim() argument
1056 indirect_offset + (is_indexed ? 12 : 8); in brw_draw_single_prim()
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| D | brw_draw.h | 79 GLsizeiptr indirect_offset,
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| /third_party/mesa3d/src/gallium/drivers/freedreno/ir3/ |
| D | ir3_const.h | 564 unsigned indirect_offset; in ir3_emit_cs_consts() local
574 if (info->indirect_offset & 0xf) { in ir3_emit_cs_consts()
578 indirect_offset = 0; in ir3_emit_cs_consts()
581 info->indirect_offset, 3); in ir3_emit_cs_consts()
584 indirect_offset = info->indirect_offset; in ir3_emit_cs_consts()
587 emit_const_prsc(ring, v, offset * 4, indirect_offset, 16, indirect); in ir3_emit_cs_consts()
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| /third_party/mesa3d/src/panfrost/midgard/ |
| D | midgard_compile.c | 1154 nir_src *indirect_offset, in emit_ubo_read() argument
1181 if (indirect_offset) { in emit_ubo_read()
1182 ins.src[2] = nir_src_index(ctx, indirect_offset); in emit_ubo_read()
1194 if (indirect_offset && indirect_offset->is_ssa && !indirect_shift) in emit_ubo_read()
1195 mir_set_ubo_offset(&ins, indirect_offset, offset); in emit_ubo_read()
1337 nir_src *indirect_offset, nir_alu_type type, bool flat) in emit_varying_read() argument
1362 if (indirect_offset) { in emit_varying_read()
1363 ins.src[2] = nir_src_index(ctx, indirect_offset); in emit_varying_read()
1751 nir_src *indirect_offset = direct ? NULL : src_offset; in emit_intrinsic() local
1762 … emit_ubo_read(ctx, &instr->instr, reg, offset, indirect_offset, 0, 0, nr_comp); in emit_intrinsic()
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| /third_party/mesa3d/src/gallium/drivers/etnaviv/tests/ |
| D | lower_ubo_tests.cpp | 169 TEST_F(nir_lower_ubo_test, indirect_offset) in TEST_F() argument
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| /third_party/mesa3d/src/intel/tools/ |
| D | i965_gram.y | 1740 $$.indirect_offset = $3.indirect_offset;
1776 $$.indirect_offset = $2;
1808 $$.indirect_offset = $3.indirect_offset;
1827 $$.indirect_offset = $3.indirect_offset;
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| /third_party/mesa3d/src/gallium/drivers/freedreno/a5xx/ |
| D | fd5_compute.c | 176 OUT_RELOC(ring, rsc->bo, info->indirect_offset, 0, 0); /* ADDR_LO/HI */ in fd5_launch_grid()
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| /third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/ |
| D | fd6_compute.c | 185 OUT_RELOC(ring, rsc->bo, info->indirect_offset, 0, 0); /* ADDR_LO/HI */ in fd6_launch_grid()
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| /third_party/mesa3d/src/gallium/drivers/softpipe/ |
| D | sp_compute.c | 153 info->indirect_offset, in fill_grid_size()
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| /third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
| D | nvc0_compute.c | 472 uint32_t offset = res->offset + info->indirect_offset; in nvc0_launch_grid()
512 uint32_t offset = res->offset + info->indirect_offset; in nvc0_compute_update_indirect_invocations()
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| /third_party/mesa3d/src/gallium/include/pipe/ |
| D | p_state.h | 980 unsigned indirect_offset; /**< must be 4 byte aligned */ member
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| /third_party/flatbuffers/dart/lib/src/ |
| D | reference.dart | 344 int _diffKeys(List<int> input, int index, int indirect_offset, int byteWidth) {
345 final keyOffset = indirect_offset + index * byteWidth;
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| /third_party/mesa3d/src/gallium/drivers/vc4/ |
| D | vc4_program.c | 95 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0); in indirect_uniform_load() local
99 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0)); in indirect_uniform_load()
100 indirect_offset = qir_MIN_NOIMM(c, indirect_offset, in indirect_uniform_load()
104 indirect_offset, in indirect_uniform_load()
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| /third_party/mesa3d/src/gallium/drivers/iris/ |
| D | iris_draw.c | 335 grid_ref->offset = grid->indirect_offset; in iris_update_grid_size_resource()
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_compute.c | 742 info->indirect_offset + 4 * i); in si_setup_nir_user_data()
835 radeon_emit(info->indirect_offset); in si_emit_dispatch_packets()
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| /third_party/mesa3d/src/gallium/drivers/crocus/ |
| D | crocus_draw.c | 457 grid_ref->offset = grid->indirect_offset; in crocus_update_grid_size_resource()
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