Searched refs:isDS (Results 1 – 11 of 11) sorted by relevance
396 } else if (instr->isDS() && instr->ds().gds) { in handle_instruction_gfx6()644 if (instr->isVMEM() || instr->isFlatLike() || instr->isDS()) { in handle_instruction_gfx10()767 } else if (instr->isDS()) { in handle_instruction_gfx10()
1100 assert(isDS()); in ds()1105 assert(isDS()); in ds()1108 constexpr bool isDS() const noexcept { return format == Format::DS; } in isDS() function
281 if (instr->isDS() && in check_instr()
698 if (candidate->isDS() || !can_move_down) { in schedule_SMEM()
2525 (instr->isDS() && instr->ds().gds)) { in register_allocation()
1139 else if (instr->isDS()) { in label_instruction()
783 (TII->isDS(MI1) && TII->isDS(MI2))) { in apply()
109 if (TII.isDS(MI.getOpcode())) { in isSendMsgTraceDataOrGDS()917 if (!SIInstrInfo::isVMEM(*I) && !SIInstrInfo::isDS(*I) && in fixVMEMtoScalarWriteHazards()1079 if (SIInstrInfo::isDS(*MI)) in fixLdsBranchVmemWARHazard()
471 static bool isDS(const MachineInstr &MI) { in isDS() function475 bool isDS(uint16_t Opcode) const { in isDS() function
542 if (TII->isDS(Inst) && (Inst.mayStore() || Inst.mayLoad())) { in updateByEvent()660 if (TII->isDS(Inst) && Inst.mayStore()) { in updateByEvent()1218 if (TII->isDS(Inst) && TII->usesLGKM_CNT(Inst)) { in updateEventWaitcntAfter()
159 if (isDS(Opc0) && isDS(Opc1)) { in areLoadsFromSameBasePtr()270 if (isDS(LdSt)) { in getMemOperandWithOffset()464 } else if (isDS(FirstLdSt) && isDS(SecondLdSt)) { in shouldClusterMemOps()2571 if (isDS(MIa)) { in areMemAccessesTriviallyDisjoint()2572 if (isDS(MIb)) in areMemAccessesTriviallyDisjoint()