| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCCodeEmitter.cpp | 207 assert(MO.isImm() && "did not expect relocated expression"); in getMachineOpValue()
218 if (MO.isImm()) in getLdStUImm12OpValue()
239 if (MO.isImm()) in getAdrLabelOpValue()
270 if (MO.isImm()) in getAddSubImmOpValue()
301 if (MO.isImm()) in getCondBranchTargetOpValue()
323 if (MO.isImm()) in getLoadLiteralOpValue()
351 if (MO.isImm()) in getMoveWideImmOpValue()
371 if (MO.isImm()) in getTestBranchTargetOpValue()
393 if (MO.isImm()) in getBranchTargetOpValue()
419 assert(MO.isImm() && "Expected an immediate value for the shift amount!"); in getVecShifterOpValue()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCCodeEmitter.cpp | 47 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
59 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
72 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
85 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
97 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
114 if (MO.isImm()) in getMemRIEncoding()
132 if (MO.isImm()) in getMemRIXEncoding()
150 if (MO.isImm()) { in getMemRIX16Encoding()
172 assert(MO.isImm()); in getSPE8DisEncoding()
187 assert(MO.isImm()); in getSPE4DisEncoding()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 62 assert(Inst.getOperand(2).isImm()); in LowerLargeShift()
242 if (MO.isImm()) return MO.getImm() >> 2; in getBranchTargetOpValue()
264 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTargetOpValue1SImm16()
286 if (MO.isImm()) in getBranchTargetOpValueMMR6()
309 if (MO.isImm()) in getBranchTargetOpValueLsl2MMR6()
332 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTarget7OpValueMM()
353 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTargetOpValueMMPC10()
374 if (MO.isImm()) return MO.getImm() >> 1; in getBranchTargetOpValueMM()
396 if (MO.isImm()) return MO.getImm() >> 2; in getBranchTarget21OpValue()
418 if (MO.isImm()) return MO.getImm() >> 2; in getBranchTarget21OpValueMM()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiMCCodeEmitter.cpp | 114 if (MCOp.isImm()) in getMachineOpValue()
145 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
153 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
194 assert((Op2.isImm() || Op2.isExpr()) && in getRiMemoryOpValue()
200 if (Op2.isImm()) { in getRiMemoryOpValue()
230 assert(AluMCOp.isImm() && "Third operator is not immediate."); in getRrMemoryOpValue()
265 assert((Op2.isImm() || Op2.isExpr()) && in getSplsOpValue()
271 if (Op2.isImm()) { in getSplsOpValue()
292 if (MCOp.isReg() || MCOp.isImm()) in getBranchTargetOpValue()
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| D | LanaiInstPrinter.cpp | 155 else if (Op.isImm()) in printOperand()
166 if (Op.isImm()) { in printMemImmOperand()
180 if (Op.isImm()) { in printHi16ImmOperand()
192 if (Op.isImm()) { in printHi16AndImmOperand()
204 if (Op.isImm()) { in printLo16AndImmOperand()
229 assert((OffsetOp.isImm() || OffsetOp.isExpr()) && "Immediate expected"); in printMemoryImmediateOffset()
230 if (OffsetOp.isImm()) { in printMemoryImmediateOffset()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCTargetDesc.cpp | 40 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && in getMCRDeprecationInfo()
41 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && in getMCRDeprecationInfo()
44 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) { in getMCRDeprecationInfo()
45 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) { in getMCRDeprecationInfo()
46 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) { in getMCRDeprecationInfo()
53 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) { in getMCRDeprecationInfo()
60 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 && in getMCRDeprecationInfo()
61 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) { in getMCRDeprecationInfo()
71 if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() && in getITDeprecationInfo()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/MCTargetDesc/ |
| D | BPFInstPrinter.cpp | 57 } else if (Op.isImm()) { in printOperand()
75 if (OffsetOp.isImm()) { in printMemOperand()
89 if (Op.isImm()) in printImm64Operand()
100 if (Op.isImm()) { in printBrTargetOperand()
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| D | BPFMCCodeEmitter.cpp | 92 if (MO.isImm()) in getMachineOpValue()
139 uint64_t Imm = MO.isImm() ? MO.getImm() : 0; in encodeInstruction()
167 assert(Op2.isImm() && "Second operand is not immediate."); in getMemoryOpValue()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/MCTargetDesc/ |
| D | MSP430MCCodeEmitter.cpp | 108 if (MO.isImm()) { in getMachineOpValue()
128 if (MO2.isImm()) { in getMemOpValue()
156 if (MO.isImm()) in getPCRelImmOpValue()
169 assert(MO.isImm() && "Expr operand expected"); in getCGImmOpValue()
188 assert(MO.isImm() && "Immediate operand expected"); in getCCOpValue()
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| D | MSP430InstPrinter.cpp | 40 if (Op.isImm()) { in printPCRelImmOperand()
58 } else if (Op.isImm()) { in printOperand()
87 assert(Disp.isImm() && "Expected immediate in displacement field"); in printSrcMemOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiMemAluCombiner.cpp | 186 (Op.isImm() && Op.getImm() == 0)); in isZeroOperand()
247 assert((AluOffset.isReg() || AluOffset.isImm()) && in insertMergedInstruction()
252 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); in insertMergedInstruction()
266 else if (AluOffset.isImm()) in insertMergedInstruction()
301 if (Op2.isImm()) { in isSuitableAluInstr()
310 if (Offset.isImm() && in isSuitableAluInstr()
375 assert(AluOperand.isImm() && "Unexpected memory operator type"); in combineMemAluInBasicBlock()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/MCTargetDesc/ |
| D | AVRMCCodeEmitter.cpp | 104 assert(MO.isImm()); in encodeRelCondBrTarget()
157 if (OffsetOp.isImm()) { in encodeMemri()
174 assert(MI.getOperand(OpNo).isImm()); in encodeComplement()
201 assert(MO.isImm()); in encodeImm()
216 assert(MO.isImm()); in encodeCallTarget()
255 if (MO.isImm()) return static_cast<unsigned>(MO.getImm()); in getMachineOpValue()
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| D | AVRInstPrinter.cpp | 116 } else if (Op.isImm()) { in printOperand()
130 if (Op.isImm()) { in printPCRelImm()
156 if (OffsetOp.isImm()) { in printMemri()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/AsmParser/ |
| D | LanaiAsmParser.cpp | 160 assert(isImm() && "Invalid type access!"); in getImm()
192 bool isImm() const override { return Kind == IMMEDIATE; } in isImm() function
209 if (!isImm()) in isBrImm()
223 bool isCallTarget() { return isImm() || isToken(); } in isCallTarget()
226 if (!isImm()) in isHiImm16()
249 if (!isImm()) in isHiImm16And()
262 if (!isImm()) in isLoImm16()
286 if (!isImm()) in isLoImm16Signed()
310 if (!isImm()) in isLoImm16And()
323 if (!isImm()) in isImmShift()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 375 bool isImm = fieldFromInstruction(insn, 13, 1); in DecodeMem() local
380 if (isImm) in DecodeMem()
398 if (isImm) in DecodeMem()
532 unsigned isImm = fieldFromInstruction(insn, 13, 1); in DecodeJMPL() local
535 if (isImm) in DecodeJMPL()
551 if (isImm) in DecodeJMPL()
565 unsigned isImm = fieldFromInstruction(insn, 13, 1); in DecodeReturn() local
568 if (isImm) in DecodeReturn()
579 if (isImm) in DecodeReturn()
594 unsigned isImm = fieldFromInstruction(insn, 13, 1); in DecodeSWAP() local
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFoldOperands.cpp | 48 if (FoldOp->isImm()) { in FoldCandidate()
62 bool isImm() const { in isImm() function
192 if (Fold.isImm()) { in updateOperand()
240 if ((Fold.isImm() || Fold.isFI() || Fold.isGlobal()) && Fold.needsShrink()) { in updateOperand()
284 if (Fold.isImm()) { in updateOperand()
358 if (Opc == AMDGPU::S_SETREG_B32 && OpToFold->isImm()) { in tryAddToFoldList()
402 (OpToFold->isImm() || OpToFold->isFI() || OpToFold->isGlobal())) { in tryAddToFoldList()
439 if (OpToFold->isImm()) { in tryAddToFoldList()
487 if (Op->isImm()) { in getRegSeqInit()
518 if (OpToFold.isImm() && TII->isInlineConstant(OpToFold, OpTy) && in tryToFoldACImm()
[all …]
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| D | GCNDPPCombine.cpp | 149 if (Op1.isImm()) in getOldOpndValue()
265 assert(OldOpnd->isImm()); in isIdentityValue()
322 if (!CombBCZ && OldOpndValue && OldOpndValue->isImm()) { in createDPPInst()
349 assert(Imm->isImm()); in hasNoImmOrEqual()
371 assert(RowMaskOpnd && RowMaskOpnd->isImm()); in combineDPPMov()
373 assert(BankMaskOpnd && BankMaskOpnd->isImm()); in combineDPPMov()
378 assert(BCZOpnd && BCZOpnd->isImm()); in combineDPPMov()
395 assert(!OldOpndValue || OldOpndValue->isImm() || OldOpndValue == OldOpnd); in combineDPPMov()
402 if (!OldOpndValue || !OldOpndValue->isImm()) { in combineDPPMov()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/MCTargetDesc/ |
| D | ARCInstPrinter.cpp | 148 if (Op.isImm()) { in printOperand()
162 assert(offset.isImm() && "Offset should be immediate."); in printMemOperandRI()
171 assert(Op.isImm() && "Predicate operand is immediate."); in printPredicateOperand()
178 assert(Op.isImm() && "Predicate operand is immediate."); in printBRCCPredicateOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/MCTargetDesc/ |
| D | SparcMCCodeEmitter.cpp | 130 if (MO.isImm()) in getMachineOpValue()
154 if (MO.isReg() || MO.isImm()) in getCallTargetOpValue()
189 if (MO.isReg() || MO.isImm()) in getBranchTargetOpValue()
202 if (MO.isReg() || MO.isImm()) in getBranchPredTargetOpValue()
215 if (MO.isReg() || MO.isImm()) in getBranchOnRegTargetOpValue()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86InstComments.cpp | 523 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
539 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
555 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
569 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
587 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
681 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
699 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
713 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
731 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
749 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/AsmParser/ |
| D | RISCVAsmParser.cpp | 276 bool isImm() const override { return Kind == KindTy::Immediate; } in isImm() function
306 if (!isImm()) in isBareSimmNLsb0()
323 if (!isImm() || evaluateConstantImm(getImm(), Imm, VK)) in isBareSymbol()
333 if (!isImm() || evaluateConstantImm(getImm(), Imm, VK)) in isCallSymbol()
344 if (!isImm() || evaluateConstantImm(getImm(), Imm, VK)) in isTPRelAddSymbol()
355 if (!isImm()) in isFenceArg()
379 if (!isImm()) in isFRMArg()
394 if (!isImm()) in isImmXLenLI()
408 if (!isImm()) in isUImmLog2XLen()
419 if (!isImm()) in isUImmLog2XLenNonZero()
[all …]
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/VE/InstPrinter/ |
| D | VEInstPrinter.cpp | 59 if (MO.isImm()) { in printOperand()
86 if (!MO.isImm() || MO.getImm() != 0) { in printMemASXOperand()
106 if (!MO.isImm() || MO.getImm() != 0) { in printMemASOperand()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 342 bool isImm() const { return Kind == CV_Immediate; } in isImm() function in __anonc2763e2e0111::CountValue
355 assert(isImm() && "Wrong CountValue accessor"); in getImm()
361 if (isImm()) { OS << Contents.ImmVal; } in print()
678 if (Op2.isImm() || Op1.getReg() == IVReg) in getLoopTripCount()
750 if (!Start->isReg() && !Start->isImm()) in computeCount()
752 if (!End->isReg() && !End->isImm()) in computeCount()
778 if (Start->isImm() && End->isImm()) { in computeCount()
850 bool RegToImm = Start->isReg() && End->isImm(); // for (reg..imm) in computeCount()
854 if (Start->isImm()) in computeCount()
856 if (End->isImm()) in computeCount()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/ |
| D | X86Operand.h | 206 bool isImm() const override { return Kind == Immediate; } in isImm() function
209 if (!isImm()) in isImmSExti16i8()
223 if (!isImm()) in isImmSExti32i8()
237 if (!isImm()) in isImmSExti64i8()
251 if (!isImm()) in isImmSExti64i32()
266 if (!isImm()) return false; in isImmUnsignedi4()
275 if (!isImm()) return false; in isImmUnsignedi8()
283 bool isOffsetOfLocal() const override { return isImm() && Imm.LocalRef; } in isOffsetOfLocal()
366 return isImm(); in isAVX512RC()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 231 bool isImm() const override { in isImm() function in __anon679113a80111::SystemZOperand
234 bool isImm(int64_t MinValue, int64_t MaxValue) const { in isImm() function in __anon679113a80111::SystemZOperand
363 bool isAnyReg() const { return (isReg() || isImm(0, 15)); } in isAnyReg()
374 bool isU1Imm() const { return isImm(0, 1); } in isU1Imm()
375 bool isU2Imm() const { return isImm(0, 3); } in isU2Imm()
376 bool isU3Imm() const { return isImm(0, 7); } in isU3Imm()
377 bool isU4Imm() const { return isImm(0, 15); } in isU4Imm()
378 bool isU6Imm() const { return isImm(0, 63); } in isU6Imm()
379 bool isU8Imm() const { return isImm(0, 255); } in isU8Imm()
380 bool isS8Imm() const { return isImm(-128, 127); } in isS8Imm()
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