| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIOptimizeExecMaskingPreRA.cpp | 88 if (ST.isWave32()) { in isEndCF()
98 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in isFullExecCopy()
111 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in getOrNonExecReg()
195 bool Wave32 = ST.isWave32(); in optimizeVcndVcmpPair()
306 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in runOnMachineFunction()
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| D | SIWholeQuadMode.cpp | 634 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(ST->isWave32() ? in toExact()
639 unsigned Exec = ST->isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in toExact()
640 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(ST->isWave32() ? in toExact()
655 unsigned Exec = ST->isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in toWQM()
660 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(ST->isWave32() ? in toWQM()
687 ST->isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC) in fromWWM()
910 unsigned Exec = ST->isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in runOnMachineFunction()
932 BuildMI(Entry, EntryMI, DebugLoc(), TII->get(ST->isWave32() ? in runOnMachineFunction()
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| D | SIRegisterInfo.h | 38 bool isWave32; variable
271 return isWave32 ? &AMDGPU::SReg_32RegClass in getBoolRC()
276 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getWaveMaskRegClass()
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| D | SIOptimizeExecMasking.cpp | 69 Src.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC)) in isCopyFromExec()
85 Dst.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC) && in isCopyToExec()
275 MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in runOnMachineFunction()
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| D | SIInsertSkips.cpp | 276 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in kill()
287 BuildMI(MBB, &MI, DL, TII->get(ST.isWave32() ? AMDGPU::S_MOV_B32 in kill()
294 if (ST.isWave32()) in kill()
347 const bool IsWave32 = ST.isWave32(); in optimizeVccBranch()
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| D | SIFrameLowering.cpp | 729 const unsigned OrSaveExec = ST.isWave32() ? in emitPrologue()
744 unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitPrologue()
745 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in emitPrologue()
889 ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 : AMDGPU::S_OR_SAVEEXEC_B64; in emitEpilogue()
902 unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitEpilogue()
903 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in emitEpilogue()
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| D | AMDGPUAtomicOptimizer.cpp | 327 if (!ST->isWave32()) { in buildScan()
370 if (!ST->isWave32()) { in buildShiftRight()
459 if (ST->isWave32()) { in optimizeAtomic()
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| D | SIRegisterInfo.cpp | 64 isWave32(ST.isWave32()) { in SIRegisterInfo()
187 if (isWave32) { in getReservedRegs()
1131 if (!isWave32) in eliminateFrameIndex()
1774 return isWave32 ? in getRegClassForSizeOnBank()
1826 return isWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC; in getVCC()
1835 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getRegClass()
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| D | SIInstrInfo.cpp | 848 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
862 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
905 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 in insertVectorSelect()
908 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
923 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 in insertVectorSelect()
926 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
1460 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64; in expandPostRAPseudo()
1461 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in expandPostRAPseudo()
1472 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64; in expandPostRAPseudo()
1473 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in expandPostRAPseudo()
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| D | SILowerControlFlow.cpp | 187 TII->isWave32() ? AMDGPU::S_MOV_B32_term : AMDGPU::S_MOV_B64_term; in getSaveExec()
507 if (ST.isWave32()) { in runOnMachineFunction()
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| D | SILowerI1Copies.cpp | 431 return MRI.createVirtualRegister(ST.isWave32() ? &AMDGPU::SReg_32RegClass in createLaneMaskReg()
462 IsWave32 = ST->isWave32(); in runOnMachineFunction()
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| D | SIAnnotateControlFlow.cpp | 143 IntMask = ST.isWave32() ? Type::getInt32Ty(Context) in initialize()
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| D | SIInstructions.td | 210 let WaveSizePredicate = isWave32 in {
376 let WaveSizePredicate = isWave32;
390 let WaveSizePredicate = isWave32;
1345 let WaveSizePredicate = isWave32;
1582 let WaveSizePredicate = isWave32 in {
1619 } // end isWave32
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| D | VOP2Instructions.td | 206 let WaveSizePredicate = isWave32 in {
247 let WaveSizePredicate = isWave32 in {
1000 let WaveSizePredicate = isWave32;
1027 let WaveSizePredicate = isWave32;
1052 let WaveSizePredicate = isWave32;
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| D | AMDGPUAsmPrinter.cpp | 392 if (MF.getSubtarget<GCNSubtarget>().isWave32()) { in getAmdhsaKernelCodeProperties()
1203 if (STM.isWave32()) in EmitPALMetadata()
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| D | AMDGPUSubtarget.h | 1180 bool isWave32() const { in isWave32() function
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| D | AMDGPURegisterBankInfo.cpp | 747 const unsigned WaveAndOpc = Subtarget.isWave32() ? in executeInWaterfallLoop()
749 const unsigned MovTermOpc = Subtarget.isWave32() ? in executeInWaterfallLoop()
751 const unsigned XorTermOpc = Subtarget.isWave32() ? in executeInWaterfallLoop()
753 const unsigned AndSaveExecOpc = Subtarget.isWave32() ? in executeInWaterfallLoop()
755 const unsigned ExecReg = Subtarget.isWave32() ? in executeInWaterfallLoop()
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| D | SIShrinkInstructions.cpp | 556 unsigned VCCReg = ST.isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC; in runOnMachineFunction()
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| D | VOPCInstructions.td | 168 let WaveSizePredicate = isWave32 in {
764 let WaveSizePredicate = isWave32 in
813 let WaveSizePredicate = isWave32 in
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| D | SIInstrInfo.h | 989 bool isWave32() const;
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| D | SIISelLowering.cpp | 3217 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_AND_SAVEEXEC_B32 in emitLoadM0FromVGPRLoop()
3254 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in emitLoadM0FromVGPRLoop()
3256 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_XOR_B32_term in emitLoadM0FromVGPRLoop()
3295 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in loadM0FromVGPR()
3296 unsigned MovExecOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in loadM0FromVGPR()
3708 bool isWave32 = getSubtarget()->isWave32(); in EmitInstrWithCustomInserter() local
3709 unsigned Exec = isWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in EmitInstrWithCustomInserter()
3714 TII->get(isWave32 ? AMDGPU::S_BFM_B32 : AMDGPU::S_BFM_B64), in EmitInstrWithCustomInserter()
3722 TII->get(isWave32 ? AMDGPU::S_CMOV_B32 : AMDGPU::S_CMOV_B64), in EmitInstrWithCustomInserter()
10755 if (ST.isWave32() && !MF.empty()) { in finalizeLowering()
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| D | AMDGPUISelDAGToDAG.cpp | 2086 Cond = SDValue(CurDAG->getMachineNode(ST->isWave32() ? AMDGPU::S_AND_B32 in SelectBRCOND()
2089 CurDAG->getRegister(ST->isWave32() ? AMDGPU::EXEC_LO in SelectBRCOND()
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| D | SIInsertWaitcnts.cpp | 1452 TII->get(ST->isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64), in insertWaitcntInBlock()
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| D | SOPInstructions.td | 170 let WaveSizePredicate = isWave32 in {
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| D | SIInstrInfo.td | 9 def isWave32 : Predicate<"Subtarget->getWavefrontSize() == 32">,
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