Searched refs:lane0 (Results 1 – 4 of 4) sorted by relevance
| /third_party/mesa3d/src/amd/llvm/ |
| D | ac_llvm_build.h | 549 LLVMValueRef ac_build_quad_swizzle(struct ac_llvm_context *ctx, LLVMValueRef src, unsigned lane0,
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| D | ac_llvm_build.c | 3499 static inline enum dpp_ctrl dpp_quad_perm(unsigned lane0, unsigned lane1, unsigned lane2, in dpp_quad_perm() argument
3502 assert(lane0 < 4 && lane1 < 4 && lane2 < 4 && lane3 < 4); in dpp_quad_perm()
3503 return _dpp_quad_perm | lane0 | (lane1 << 2) | (lane2 << 4) | (lane3 << 6); in dpp_quad_perm()
4344 LLVMValueRef ac_build_quad_swizzle(struct ac_llvm_context *ctx, LLVMValueRef src, unsigned lane0, in ac_build_quad_swizzle() argument
4347 unsigned mask = dpp_quad_perm(lane0, lane1, lane2, lane3); in ac_build_quad_swizzle()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 21.0.0.rst | 320 - pan/bi: Use consistent naming of lane/lane0
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| D | 21.2.0.rst | 2753 - pan/bi: Replace lane0 modifier with lane_dest for load instructions
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