| /third_party/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_emit.h | 38 uint32_t last_reg; member
148 coalesce->last_reg = 0; in etna_coalesce_start()
176 if (coalesce->last_reg != 0) { in check_coalsence()
177 if (((coalesce->last_reg + 4) != reg) || (coalesce->last_fixp != fixp)) { in check_coalsence()
187 coalesce->last_reg = reg; in check_coalsence()
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_pm4.c | 82 if (opcode != state->last_opcode || reg != (state->last_reg + 1)) { in si_pm4_set_reg()
87 state->last_reg = reg; in si_pm4_set_reg()
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| D | si_pm4.h | 49 unsigned last_reg; member
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.td | 42 class RegSeqNames<int last_reg, int stride, int size, string prefix,
47 !if(!le(end_reg, last_reg),
49 RegSeqNames<last_reg, stride, size, prefix, next>.ret),
54 class RegSeqDags<RegisterClass RC, int last_reg, int stride, int size,
58 !add(!add(last_reg, 2), !mul(size, -1)),
59 !add(last_reg, 1)));
63 RegSeqDags<RC, last_reg, stride, size, !add(start, 1)>.ret),
68 int last_reg, int stride, int size, string prefix> :
70 RegSeqDags<RC, last_reg, stride, size>.ret,
71 RegSeqNames<last_reg, stride, size, prefix>.ret>;
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| /third_party/boost/boost/move/algo/detail/ |
| D | adaptive_sort_merge.hpp | 944 RandIt const last_reg = first_reg + l_block; in op_merge_blocks_with_irreg() local
948 BOOST_MOVE_ADAPTIVE_SORT_INVARIANT(boost::movelib::is_sorted(first_reg, last_reg, comp)); in op_merge_blocks_with_irreg()
953 …dest = next_key_idx ? op_partial_merge_and_swap(first_irr, last_irr, first_reg, last_reg, first_mi… in op_merge_blocks_with_irreg()
954 … : op_partial_merge (first_irr, last_irr, first_reg, last_reg, dest, comp, op, is_stable); in op_merge_blocks_with_irreg()
959 : last_reg; in op_merge_blocks_with_irreg()
962 dest = next_key_idx ? op(three_way_forward_t(), first_reg, last_reg, first_min, dest) in op_merge_blocks_with_irreg()
963 : op(forward_t(), first_reg, last_reg, dest); in op_merge_blocks_with_irreg()
967 swap_and_update_key(key_next, key_first, key_mid, last_reg, last_reg, first_min); in op_merge_blocks_with_irreg()
970 first_reg = last_reg; in op_merge_blocks_with_irreg()
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| /third_party/mesa3d/src/freedreno/ir3/ |
| D | ir3_validate.c | 166 struct ir3_register *last_reg = NULL; in validate_instr() local
203 validate_assert(ctx, (last_reg->flags & IR3_REG_HALF) == in validate_instr()
207 last_reg = reg; in validate_instr()
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| /third_party/ltp/tools/sparse/sparse-src/ |
| D | example.c | 97 static int last_reg, stack_offset; variable
502 i = last_reg; in target_reg()
510 last_reg = i; in target_reg()
513 } while (i != last_reg); in target_reg()
532 last_reg = i; in find_in_reg()
1914 last_reg = -1; in output()
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| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_vec4.cpp | 404 unsigned last_reg = ~0u, last_offset = ~0u; in opt_vector_float() local
437 last_reg = ~0u; in opt_vector_float()
444 if (last_reg != inst->dst.nr || in opt_vector_float()
465 last_reg = ~0u;; in opt_vector_float()
488 last_reg = inst->dst.nr; in opt_vector_float()
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| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_register_allocation.cpp | 455 PhysReg last_reg = first_reg.advance(size_id.first - 1); in print_regs() local
456 if (first_reg.reg() != last_reg.reg()) { in print_regs()
457 assert(first_reg.byte() == 0 && last_reg.byte() == 3); in print_regs()
458 printf("-%d", last_reg.reg() - regs.lo()); in print_regs()
461 if (first_reg.byte() != 0 || last_reg.byte() != 3) { in print_regs()
462 printf("[%d:%d]", first_reg.byte() * 8, (last_reg.byte() + 1) * 8); in print_regs()
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