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Searched refs:max_dw (Results 1 – 14 of 14) sorted by relevance

/third_party/mesa3d/src/amd/vulkan/
Dradv_cs.h37 if (cs->max_dw - cs->cdw < needed) in radeon_check_space()
46 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_config_reg_seq()
63 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_context_reg_seq()
80 assert(cs->cdw + 3 <= cs->max_dw); in radeon_set_context_reg_idx()
90 assert(cs->cdw + 4 <= cs->max_dw); in radeon_set_context_reg_rmw()
101 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_sh_reg_seq()
119 assert(cs->cdw + 3 <= cs->max_dw); in radeon_set_sh_reg_idx()
135 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_uconfig_reg_seq()
145 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_uconfig_reg_seq_perfctr()
163 assert(cs->cdw + 3 <= cs->max_dw); in radeon_set_uconfig_reg_idx()
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Dradv_radeon_winsys.h95 unsigned max_dw; /* Maximum number of dwords. */ member
Dradv_pipeline.c5340 cs->max_dw = 64; in radv_pipeline_generate_pm4()
5341 ctx_cs->max_dw = 256; in radv_pipeline_generate_pm4()
5342 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw)); in radv_pipeline_generate_pm4()
5343 ctx_cs->buf = cs->buf + cs->max_dw; in radv_pipeline_generate_pm4()
5374 assert(ctx_cs->cdw <= ctx_cs->max_dw); in radv_pipeline_generate_pm4()
5375 assert(cs->cdw <= cs->max_dw); in radv_pipeline_generate_pm4()
5705 cs->max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 19 : 16; in radv_compute_generate_pm4()
5706 cs->buf = malloc(cs->max_dw * 4); in radv_compute_generate_pm4()
5711 assert(pipeline->cs.cdw <= pipeline->cs.max_dw); in radv_compute_generate_pm4()
/third_party/mesa3d/src/gallium/drivers/r600/
Dr600_cs.h134 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_config_reg_seq()
148 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_context_reg_seq()
164 assert(cs->current.cdw + 3 <= cs->current.max_dw); in radeon_set_context_reg_idx()
173 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_sh_reg_seq()
187 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_uconfig_reg_seq()
203 assert(cs->current.cdw + 3 <= cs->current.max_dw); in radeon_set_uconfig_reg_idx()
Dr600_pipe.h626 assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw); in r600_emit_command_buffer()
999 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_ctl_const_seq()
Dr600_pipe_common.c270 assert((num_dw + ctx->dma.cs.current.cdw) <= ctx->dma.cs.current.max_dw); in r600_need_dma_space()
/third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_cs.c231 cs->base.max_dw = ib_size / 4 - 4; in radv_amdgpu_cs_create()
243 cs->base.max_dw = 4096; in radv_amdgpu_cs_create()
261 uint64_t ib_dws = MAX2(cs->base.cdw + min_size, MIN2(cs->base.max_dw * 2, limit_dws)); in radv_amdgpu_cs_grow()
279 cs->old_cs_buffers[cs->num_old_cs_buffers].max_dw = cs->base.max_dw; in radv_amdgpu_cs_grow()
288 ib_dws = MAX2(cs->base.cdw + min_size, MIN2(cs->base.max_dw * 2, limit_dws)); in radv_amdgpu_cs_grow()
300 cs->base.max_dw = ib_dws; in radv_amdgpu_cs_grow()
308 uint64_t ib_size = MAX2(min_size * 4 + 16, cs->base.max_dw * 4 * 2); in radv_amdgpu_cs_grow()
366 cs->base.max_dw = ib_size / 4 - 4; in radv_amdgpu_cs_grow()
570 if (parent->base.cdw + 4 > parent->base.max_dw) in radv_amdgpu_cs_execute_secondary()
585 if (parent->base.cdw + ib->cdw > parent->base.max_dw) in radv_amdgpu_cs_execute_secondary()
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/third_party/mesa3d/docs/relnotes/
D12.0.1.rst39 - radeon: reference the correct cdw/max_dw
/third_party/mesa3d/src/amd/vulkan/winsys/null/
Dradv_null_cs.c78 cs->base.max_dw = 4096; in radv_null_cs_create()
/third_party/mesa3d/src/gallium/winsys/amdgpu/drm/
Damdgpu_cs.c818 rcs->current.max_dw = ib_size / 4 - amdgpu_cs_epilog_dws(cs); in amdgpu_get_new_ib()
1081 assert(rcs->current.cdw <= rcs->current.max_dw); in amdgpu_cs_check_space()
1097 if (rcs->current.max_dw - rcs->current.cdw >= dw) in amdgpu_cs_check_space()
1128 rcs->current.max_dw += cs_epilog_dw; in amdgpu_cs_check_space()
1142 assert(rcs->current.cdw <= rcs->current.max_dw); in amdgpu_cs_check_space()
1151 rcs->prev[rcs->num_prev].max_dw = rcs->current.cdw; /* no modifications */ in amdgpu_cs_check_space()
1158 rcs->current.max_dw = ib->big_ib_buffer->size / 4 - cs_epilog_dw; in amdgpu_cs_check_space()
1666 rcs->current.max_dw += amdgpu_cs_epilog_dws(cs); in amdgpu_cs_flush()
1712 if (rcs->current.cdw > rcs->current.max_dw) { in amdgpu_cs_flush()
1718 rcs->current.cdw <= rcs->current.max_dw && in amdgpu_cs_flush()
/third_party/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_cs.c211 rcs->current.max_dw = ARRAY_SIZE(cs->csc->buf); in radeon_drm_cs_create()
458 assert(rcs->current.cdw <= rcs->current.max_dw); in radeon_drm_cs_check_space()
459 return rcs->current.max_dw - rcs->current.cdw >= dw; in radeon_drm_cs_check_space()
610 if (rcs->current.cdw > rcs->current.max_dw) { in radeon_drm_cs_flush()
650 if (rcs->current.cdw && rcs->current.cdw <= rcs->current.max_dw && in radeon_drm_cs_flush()
/third_party/mesa3d/src/gallium/drivers/r300/
Dr300_cs.h49 assert(size <= (cs_copy->current.max_dw - cs_copy->current.cdw)); \
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_build_pm4.h57 assert(__cs->current.cdw <= __cs->current.max_dw); \
/third_party/mesa3d/src/gallium/drivers/radeon/
Dradeon_winsys.h198 unsigned max_dw; /* Maximum number of dwords. */ member