Searched refs:midgard_reg_mode_8 (Results 1 – 5 of 5) sorted by relevance
136 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()141 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()146 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()151 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()155 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()377 case midgard_reg_mode_8: in bits_for_mode()444 bool is_vec16 = reg_mode == midgard_reg_mode_8; in print_vec_selectors()530 if (mode == midgard_reg_mode_8 || mode == midgard_reg_mode_16) in print_vec_swizzle()841 bool shrinkable = (mode != midgard_reg_mode_8); in print_vector_field()
146 case midgard_reg_mode_8: in mir_print_constant_component()
254 midgard_reg_mode_8 = 0, enumerator
201 #define M8 midgard_reg_mode_8
322 } else if (reg_mode == midgard_reg_mode_8) { in mir_pack_swizzle()