| /third_party/mesa3d/src/amd/compiler/tests/ |
| D | test_insert_nops.cpp | 36 aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>( in create_mimg() local
38 mimg->definitions[0] = Definition(PhysReg(256), v1); in create_mimg()
39 mimg->operands[0] = Operand(PhysReg(0), s8); in create_mimg()
40 mimg->operands[1] = Operand(PhysReg(0), s4); in create_mimg()
41 mimg->operands[2] = Operand(v1); in create_mimg()
43 mimg->operands[3 + i] = Operand(PhysReg(256 + (nsa ? i * 2 : i)), v1); in create_mimg()
44 mimg->dmask = 0x1; in create_mimg()
45 mimg->dim = ac_image_2d; in create_mimg()
47 assert(get_mimg_nsa_dwords(mimg.get()) + 2 == instr_dwords); in create_mimg()
49 bld.insert(std::move(mimg)); in create_mimg()
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| D | test_hard_clause.cpp | 70 aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>( in create_mimg() local
72 mimg->definitions[0] = Definition(PhysReg(256), v1); in create_mimg()
73 mimg->operands[0] = Operand(desc); in create_mimg()
74 mimg->operands[0].setFixed(PhysReg(0)); in create_mimg()
75 mimg->operands[1] = Operand(PhysReg(0), s4); in create_mimg()
76 mimg->operands[2] = Operand(v1); in create_mimg()
78 mimg->operands[3 + i] = Operand(PhysReg(256 + (nsa ? i * 2 : i)), v1); in create_mimg()
79 mimg->dmask = 0x1; in create_mimg()
80 mimg->dim = ac_image_2d; in create_mimg()
82 bld.insert(std::move(mimg)); in create_mimg()
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| /third_party/pixman/demos/ |
| D | convolution-test.c | 24 pixman_image_t *simg, *mimg, *dimg; in main() local
36 mimg = pixman_image_create_bits (PIXMAN_a8r8g8b8, WIDTH, HEIGHT, mask, WIDTH * 4); in main()
39 pixman_image_set_filter (mimg, PIXMAN_FILTER_CONVOLUTION, in main()
42 pixman_image_composite (PIXMAN_OP_OVER, simg, mimg, dimg, 0, 0, 0, 0, 0, 0, WIDTH, HEIGHT); in main()
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| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_print_ir.cpp | 390 const MIMG_instruction& mimg = instr->mimg(); in print_instr_format_specific() local
393 if ((mimg.dmask & identity_dmask) != identity_dmask) in print_instr_format_specific()
394 fprintf(output, " dmask:%s%s%s%s", mimg.dmask & 0x1 ? "x" : "", in print_instr_format_specific()
395 mimg.dmask & 0x2 ? "y" : "", mimg.dmask & 0x4 ? "z" : "", in print_instr_format_specific()
396 mimg.dmask & 0x8 ? "w" : ""); in print_instr_format_specific()
397 switch (mimg.dim) { in print_instr_format_specific()
407 if (mimg.unrm) in print_instr_format_specific()
409 if (mimg.glc) in print_instr_format_specific()
411 if (mimg.dlc) in print_instr_format_specific()
413 if (mimg.slc) in print_instr_format_specific()
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| D | aco_assembler.cpp | 456 MIMG_instruction& mimg = instr->mimg(); in emit_instruction() local
458 encoding |= mimg.slc ? 1 << 25 : 0; in emit_instruction()
461 encoding |= mimg.lwe ? 1 << 17 : 0; in emit_instruction()
462 encoding |= mimg.tfe ? 1 << 16 : 0; in emit_instruction()
463 encoding |= mimg.glc ? 1 << 13 : 0; in emit_instruction()
464 encoding |= mimg.unrm ? 1 << 12 : 0; in emit_instruction()
466 assert(!mimg.dlc); /* Device-level coherent is not supported on GFX9 and lower */ in emit_instruction()
467 assert(!mimg.r128); in emit_instruction()
468 encoding |= mimg.a16 ? 1 << 15 : 0; in emit_instruction()
469 encoding |= mimg.da ? 1 << 14 : 0; in emit_instruction()
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| D | aco_opt_value_numbering.cpp | 259 MIMG_instruction& aM = a->mimg(); in operator ()()
260 MIMG_instruction& bM = b->mimg(); in operator ()()
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| D | aco_instruction_selection.cpp | 5992 aco_ptr<MIMG_instruction> mimg{ in emit_mimg() local
5995 mimg->definitions[0] = dst; in emit_mimg()
5996 mimg->operands[0] = Operand(rsrc); in emit_mimg()
5997 mimg->operands[1] = samp; in emit_mimg()
5998 mimg->operands[2] = vdata; in emit_mimg()
6000 mimg->operands[3 + i] = Operand(coords[i]); in emit_mimg()
6002 MIMG_instruction* res = mimg.get(); in emit_mimg()
6003 bld.insert(std::move(mimg)); in emit_mimg()
6033 MIMG_instruction* mimg = emit_mimg(bld, aco_opcode::image_bvh64_intersect_ray, Definition(dst), in visit_bvh64_intersect_ray_amd() local
6035 mimg->dim = ac_image_1d; in visit_bvh64_intersect_ray_amd()
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| D | aco_ir.cpp | 174 case Format::MIMG: return instr->mimg().sync; in get_sync_info()
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| D | aco_ir.h | 1131 MIMG_instruction& mimg() noexcept in mimg() function
1136 const MIMG_instruction& mimg() const noexcept in mimg() function
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| D | aco_insert_exec_mask.cpp | 107 return instr->mimg().disable_wqm; in needs_exact()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | MIMGInstructions.td | 83 class mimg <bits<8> si_gfx10, bits<8> vi = si_gfx10> {
415 class MIMG_Atomic_si<mimg op, string asm, RegisterClass data_rc,
422 class MIMG_Atomic_vi<mimg op, string asm, RegisterClass data_rc,
429 class MIMG_Atomic_gfx10<mimg op, string opcode,
443 class MIMG_Atomic_nsa_gfx10<mimg op, string opcode,
459 multiclass MIMG_Atomic_Addr_Helper_m <mimg op, string asm,
491 multiclass MIMG_Atomic <mimg op, string asm, bit isCmpSwap = 0> { // 64-bit atomics
710 defm IMAGE_ATOMIC_SWAP : MIMG_Atomic <mimg<0x0f, 0x10>, "image_atomic_swap">;
711 defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic <mimg<0x10, 0x11>, "image_atomic_cmpswap", 1>;
712 defm IMAGE_ATOMIC_ADD : MIMG_Atomic <mimg<0x11, 0x12>, "image_atomic_add">;
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| D | AMDGPU.td | 36 def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
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