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Searched refs:ndw (Results 1 – 25 of 30) sorted by relevance

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/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_pm4.c32 assert(state->ndw < SI_PM4_MAX_DW); in si_pm4_cmd_begin()
34 state->last_pm4 = state->ndw++; in si_pm4_cmd_begin()
39 assert(state->ndw < SI_PM4_MAX_DW); in si_pm4_cmd_add()
40 state->pm4[state->ndw++] = dw; in si_pm4_cmd_add()
47 count = state->ndw - state->last_pm4 - 2; in si_pm4_cmd_end()
80 assert(state->ndw + 2 <= SI_PM4_MAX_DW); in si_pm4_set_reg()
84 state->pm4[state->ndw++] = reg; in si_pm4_set_reg()
88 state->pm4[state->ndw++] = val; in si_pm4_set_reg()
94 state->ndw = 0; in si_pm4_clear_state()
126 radeon_emit_array(state->pm4, state->ndw); in si_pm4_emit()
Dsi_pm4.h53 unsigned ndw; member
Dsi_cp_reg_shadowing.c193 shadowing_preamble->ndw); in si_init_cp_reg_shadowing()
Dsi_debug.c417 ac_parse_ib(f, ctx->cs_preamble_state->pm4, ctx->cs_preamble_state->ndw, NULL, 0, in si_log_chunk_type_cs_print()
421 ac_parse_ib(f, ctx->cs_preamble_gs_rings->pm4, ctx->cs_preamble_gs_rings->ndw, NULL, 0, in si_log_chunk_type_cs_print()
/third_party/mesa3d/src/gallium/drivers/r600/sb/
Dsb_core.cpp120 bc_dump(*sh, bc->bytecode, bc->ndw).run(); in r600_sb_bytecode_process()
129 sh->src_stats.ndw = bc->ndw; in r600_sb_bytecode_process()
259 bc->ndw = nbc.ndw(); in r600_sb_bytecode_process()
260 bc->bytecode = (uint32_t*) malloc(bc->ndw << 2); in r600_sb_bytecode_process()
275 sh->opt_stats.ndw = bc->ndw; in r600_sb_bytecode_process()
Dsb_bc_decoder.cpp35 assert(i+1 <= ndw); in decode_cf()
114 assert(i <= ndw); in decode_cf_alu()
179 assert(i <= ndw); in decode_cf_exp()
233 assert(i <= ndw); in decode_cf_mem()
294 assert(i <= ndw); in decode_alu()
409 assert(i + 4 <= ndw); in decode_fetch()
508 assert(i <= ndw); in decode_fetch_gds()
544 assert(i <= ndw); in decode_fetch_mem()
585 assert(i <= ndw); in decode_fetch_vtx()
Dsb_bc.h635 unsigned ndw; member
648 shader_stats() : ndw(), ngpr(), nstack(), cf(), alu(), alu_clauses(), in shader_stats()
793 unsigned ndw; variable
798 : ctx(sctx), dw(data), ndw(size) {} in bc_decoder()
952 unsigned ndw() { return bc.size(); } in ndw() function
982 if (pos == ndw()) {
Dsb_bc_dump.cpp443 s << "===== " << ndw << " dw ===== " << sh.ngpr in init()
468 vpass(s), bc_data(), ndw(), id(), in bc_dump()
473 ndw = bc->ndw(); in bc_dump()
573 assert(dw_id + count <= ndw); in dump_dw()
Dsb_bc_builder.cpp71 bb.seek(bb.ndw()); in build()
72 cf->bc.addr = bb.ndw() >> 1; in build()
74 cf->bc.count = (bb.ndw() >> 1) - cf->bc.addr - 1; in build()
77 bb.seek(bb.ndw()); in build()
78 cf->bc.addr = bb.ndw() >> 1; in build()
80 cf->bc.count = (((bb.ndw() >> 1) - cf->bc.addr) >> 1) - 1; in build()
122 bb.seek(bb.ndw()); in build_alu_group()
Dsb_shader.cpp640 ndw += s.ndw; in accumulate()
653 sblog << "dw:" << ndw << ", gpr:" << ngpr << ", stk:" << nstack in dump()
675 sblog << "dw:"; print_diff(ndw, s.ndw); in dump_diff()
Dsb_pass.h91 unsigned ndw; variable
101 bc_dump(shader &s, uint32_t *bc_ptr, unsigned ndw) : in bc_dump() argument
102 vpass(s), bc_data(bc_ptr), ndw(ndw), id(), new_group(), group_index() {} in bc_dump()
/third_party/libdrm/radeon/
Dradeon_cs.c7 radeon_cs_create(struct radeon_cs_manager *csm, uint32_t ndw) in radeon_cs_create() argument
9 struct radeon_cs_int *csi = csm->funcs->cs_create(csm, ndw); in radeon_cs_create()
28 radeon_cs_begin(struct radeon_cs *cs, uint32_t ndw, in radeon_cs_begin() argument
32 return csi->csm->funcs->cs_begin(csi, ndw, file, func, line); in radeon_cs_begin()
Dradeon_cs_int.h16 unsigned ndw; member
37 uint32_t ndw);
44 uint32_t ndw,
Dradeon_cs_gem.c126 uint32_t ndw) in cs_gem_create() argument
131 if (ndw > (64 * 1024 / 4)) { in cs_gem_create()
139 csg->base.ndw = 64 * 1024 / 4; in cs_gem_create()
277 uint32_t ndw, in cs_gem_begin() argument
290 cs->section_ndw = ndw; in cs_gem_begin()
296 if (cs->cdw + ndw > cs->ndw) { in cs_gem_begin()
300 tmp = (cs->cdw + ndw + 0x3FF) & (~0x3FF); in cs_gem_begin()
306 cs->ndw = tmp; in cs_gem_begin()
Dradeon_cs.h56 unsigned ndw; member
66 uint32_t ndw);
69 uint32_t ndw,
/third_party/mesa3d/src/gallium/drivers/r600/
Dr600_asm.c176 bc->ndw += 2; in r600_bytecode_add_cf()
181 bc->ndw += 2; in r600_bytecode_add_cf()
930 bc->cf_last->ndw -= align(prev_nliteral, 2); in merge_inst_groups()
1149 if ((bc->cf_last->ndw>>1) >= 110) in load_ar_r6xx()
1180 if ((bc->cf_last->ndw>>1) >= 110) in load_ar()
1276 bc->cf_last->ndw += 2; in r600_bytecode_add_alu_type()
1277 bc->ndw += 2; in r600_bytecode_add_alu_type()
1312 bc->cf_last->ndw += align(nliteral, 2); in r600_bytecode_add_alu_type()
1316 if ((bc->cf_last->ndw >> 1) >= 120) { in r600_bytecode_add_alu_type()
1417 bc->cf_last->ndw += 4; in r600_bytecode_add_vtx_internal()
[all …]
Dr600_asm.h194 unsigned ndw; member
263 unsigned ndw; member
Deg_asm.c70 S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1); in eg_bytecode_cf_build()
77 S_SQ_CF_WORD1_COUNT((cf->ndw / 4) - 1); in eg_bytecode_cf_build()
Dr700_asm.c28 unsigned count = (cf->ndw / 4) - 1; in r700_bytecode_cf_vtx_build()
Devergreen_compute.c413 bc->ndw = binary->code_size / 4; in r600_create_shader()
458 shader->bc.ndw * 4); in evergreen_create_compute_state()
463 memcpy(p, shader->bc.bytecode, shader->bc.ndw * 4); in evergreen_create_compute_state()
/third_party/libdrm/tests/amdgpu/
Dcs_tests.c149 static int submit(unsigned ndw, unsigned ip) in submit() argument
158 ib_info.size = ndw; in submit()
Dvcn_tests.c181 static int submit(unsigned ndw, unsigned ip) in submit() argument
190 ib_info.size = ndw; in submit()
Duvd_enc_tests.c153 static int submit(unsigned ndw, unsigned ip) in submit() argument
162 ib_info.size = ndw; in submit()
Dvce_tests.c195 static int submit(unsigned ndw, unsigned ip) in submit() argument
204 ib_info.size = ndw; in submit()
/third_party/mesa3d/src/gallium/drivers/r600/sfn/
Dsfn_ir_to_assembly.cpp958 if (m_bc->cf_last->ndw > 240 - 4 * n_values) in visit()
999 if (m_bc->cf_last->ndw > 240 - 4) in visit()
1085 if ((m_bc->cf_last->ndw>>1) >= 110) in emit_index_reg()

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