| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_nir_lower_alpha_to_coverage.c | 68 nir_iand_imm(b, nir_ushr(b, nir_imm_int(b, 0xfea80), in build_dither_mask()
69 nir_iand_imm(b, m, ~3)), in build_dither_mask()
72 nir_ssa_def *part_b = nir_iand_imm(b, m, 2); in build_dither_mask()
73 nir_ssa_def *part_c = nir_iand_imm(b, m, 1); in build_dither_mask()
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| D | brw_nir_lower_shader_calls.c | 155 nir_ssa_def *cull_mask = nir_iand_imm(b, call->src[2].ssa, 0xff); in lower_shader_calls_instr()
156 nir_ssa_def *sbt_offset = nir_iand_imm(b, call->src[3].ssa, 0xf); in lower_shader_calls_instr()
157 nir_ssa_def *sbt_stride = nir_iand_imm(b, call->src[4].ssa, 0xf); in lower_shader_calls_instr()
158 nir_ssa_def *miss_index = nir_iand_imm(b, call->src[5].ssa, 0xffff); in lower_shader_calls_instr()
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| D | brw_nir_lower_rt_intrinsics.c | 277 sysval = nir_iand_imm(b, geometry_index_dw, BITFIELD_MASK(29)); in lower_rt_intrinsics_impl()
359 sysval = nir_i2b(b, nir_iand_imm(b, flags_dw, 1u << 30)); in lower_rt_intrinsics_impl()
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| D | brw_nir_rt.c | 229 nir_i2b(b, nir_iand_imm(b, nir_load_ray_flags(b), in build_terminate_ray()
308 nir_i2b(&b, nir_iand_imm(&b, nir_load_ray_flags(&b), in lower_ray_walk_intrinsics()
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| D | brw_nir_rt_builder.h | 221 defs->num_dss_rt_stacks = nir_iand_imm(b, nir_channel(b, data, 5), 0xffff); in brw_nir_rt_load_globals()
294 defs->front_face = nir_i2b(b, nir_iand_imm(b, bitfield, 1 << 27)); in brw_nir_rt_load_mem_hit()
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| /third_party/mesa3d/src/compiler/nir/ |
| D | nir_lower_ubo_vec4.c | 131 nir_iand_imm(b, in nir_lower_ubo_vec4_lower()
146 nir_i2b(b, nir_iand_imm(b, byte_offset, 8)), in nir_lower_ubo_vec4_lower()
166 nir_iand_imm(b, in nir_lower_ubo_vec4_lower()
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| D | nir_lower_texcoord_replace.c | 127 nir_i2b(&b, nir_iand_imm(&b, mask, coord_replace)); in nir_lower_texcoord_replace_impl()
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| D | nir_opt_idiv_const.c | 116 return nir_isub(b, n, nir_iand_imm(b, tmp, -d)); in build_irem()
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| D | nir_format_convert.h | 457 mantissa = nir_iadd(b, nir_iand_imm(b, mantissa, 1), in nir_format_pack_r9g9b9e5()
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| D | nir_lower_double_ops.c | 180 nir_ssa_def *even = nir_iand_imm(b, unbiased_exp, 1); in lower_sqrt_rsq()
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| D | nir_lower_int64.c | 1166 nir_u2u32(b, nir_iand_imm(b, x, 0xffffff)); in lower_scan_iadd64()
1168 nir_u2u32(b, nir_iand_imm(b, nir_ushr(b, x, nir_imm_int(b, 24)), in lower_scan_iadd64()
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| D | nir_lower_subgroups.c | 666 return nir_i2b(b, nir_iand_imm(b, nir_ushr(b, int_val, idx), 1)); in lower_subgroups_instr()
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| D | nir_lower_tex.c | 1232 new_sample = nir_iand_imm(b, &fmask_fetch->dest.ssa, 0xf); in nir_lower_ms_txf_to_fragment_fetch()
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| D | nir_builder.h | 910 nir_iand_imm(nir_builder *build, nir_ssa_def *x, uint64_t y) in nir_iand_imm() function
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| /third_party/mesa3d/src/panfrost/lib/ |
| D | pan_indirect_draw.c | 448 nir_ior(b, nir_iand_imm(b, draw_w0, 0xffff), in update_job()
470 *d = nir_iand_imm(b, nir_u2u32(b, fi), ~(1 << 31)); in split_div()
490 w0 = nir_iand_imm(b, nir_channel(b, w01, 0), ~type_mask); in update_vertex_attrib_buf()
693 nir_iand_imm(b, nir_iadd_imm(b, size, 63), ~63); in update_varying_buf()
814 val = nir_ior(b, nir_iand_imm(b, val, 0xffffff01), in set_null_job()
849 nir_ssa_def *offset = nir_iand_imm(b, nir_unpack_64_2x32_split_x(b, base), 3); in get_instance_size()
853 nir_ssa_def *aligned_end = nir_iand_imm(b, end, ~3); in get_instance_size()
873 nir_ssa_def *data = nir_iand_imm(b, val, mask); in get_instance_size()
898 nir_ssa_def *data = nir_iand_imm(b, val, mask); in get_instance_size()
1013 nir_ssa_def *start = nir_iand_imm(b, nir_unpack_64_2x32_split_x(b, base), 3); in get_index_min_max()
[all …]
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| D | pan_indirect_dispatch.c | 192 nir_ssa_def *num_wg_x_split = nir_iand_imm(&b, nir_ushr_imm(&b, split, 10), 0x3f); in GENX()
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| /third_party/mesa3d/src/gallium/drivers/v3d/ |
| D | v3d_blit.c | 701 nir_ishl(&b, nir_iand_imm(&b, x, 1), two); in v3d_get_sand8_fs()
703 nir_ishl(&b, nir_iand_imm(&b, x, 60), one); in v3d_get_sand8_fs()
713 nir_ishl(&b, nir_iand_imm(&b, x, 2), six), in v3d_get_sand8_fs()
721 nir_ishl(&b, nir_iand_imm(&b, x, 31), two)); in v3d_get_sand8_fs()
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| /third_party/mesa3d/src/amd/common/ |
| D | ac_nir_lower_esgs_io_to_mem.c | 187 return nir_iand_imm(b, vertex_offset, 0xffffu); in gs_per_vertex_input_vertex_offset_gfx9()
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| D | ac_nir_lower_ngg.c | 1430 nir_ssa_def *swizzle = nir_iand_imm(b, row, (1u << write_stride_2exp) - 1u); in ngg_gs_out_vertex_addr()
1605 nir_ssa_def *odd = nir_iand_imm(b, current_vtx_per_prim, 1); in lower_ngg_gs_emit_vertex_with_counter()
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| D | ac_surface.c | 3057 nir_ssa_def *pipeXor = nir_iand_imm(b, nir_ishl(b, nir_iand_imm(b, pipe_xor, pipeMask), in gfx10_nir_meta_addr_from_coord()
3132 nir_ssa_def *pipeXor = nir_iand_imm(b, pipe_xor, (1 << numPipeBits) - 1); in gfx9_nir_meta_addr_from_coord()
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| /third_party/mesa3d/src/panfrost/vulkan/ |
| D | panvk_vX_meta_copy.c | 464 rg = nir_iand_imm(&b, rg, 255); in panvk_meta_copy_img2img_shader()
1025 nir_iand_imm(&b, texel, BITFIELD_MASK(5)), in panvk_meta_copy_buf2img_shader()
1026 nir_iand_imm(&b, nir_ushr_imm(&b, texel, 5), BITFIELD_MASK(6)), in panvk_meta_copy_buf2img_shader()
1027 nir_iand_imm(&b, nir_ushr_imm(&b, texel, 11), BITFIELD_MASK(5))); in panvk_meta_copy_buf2img_shader()
1539 nir_ishl(&b, nir_iand_imm(&b, nir_channel(&b, texel, i), 0xff), in panvk_meta_copy_img2buf_shader()
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| /third_party/mesa3d/docs/relnotes/ |
| D | 20.3.0.rst | 2625 - nir/builder: Add a nir_iand_imm helper
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