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Searched refs:num_subslices (Results 1 – 6 of 6) sorted by relevance

/third_party/mesa3d/src/intel/dev/
Dintel_device_info.c97 .num_subslices = { 1, },
119 .num_subslices = { 1, },
139 .num_subslices = { 1, },
162 .num_subslices = { 1, },
192 .num_subslices = { 1, },
228 .num_subslices = { 1, },
256 .num_subslices = { 1, },
285 .num_subslices = { 1, },
320 .num_subslices = { 1, },
348 .num_subslices = { 2, },
[all …]
Dintel_device_info_test.c40 for (uint32_t s = 0; s < ARRAY_SIZE(devinfo.num_subslices); s++) in main()
41 assert(devinfo.num_subslices[s] <= devinfo.max_subslices_per_slice); in main()
Dintel_device_info.h147 unsigned num_subslices[INTEL_DEVICE_MAX_SUBSLICES]; member
/third_party/mesa3d/src/intel/tools/
Dintel_noop_drm_shim.c205 *gp->value += i915.devinfo.num_subslices[s]; in i915_ioctl_get_param()
210 *gp->value += i915.devinfo.num_subslices[s] * i915.devinfo.num_eu_per_subslice; in i915_ioctl_get_param()
231 i915.devinfo.num_slices * DIV_ROUND_UP(i915.devinfo.num_subslices[0], 8) + in query_write_topology()
232 i915.devinfo.num_slices * i915.devinfo.num_subslices[0] * in query_write_topology()
251 info->max_subslices = i915.devinfo.num_subslices[0]; in query_write_topology()
255 info->subslice_stride = DIV_ROUND_UP(i915.devinfo.num_subslices[0], 8); in query_write_topology()
263 uint32_t subslice_mask = (1u << i915.devinfo.num_subslices[s]) - 1; in query_write_topology()
271 for (uint32_t ss = 0; ss < i915.devinfo.num_subslices[s]; ss++) { in query_write_topology()
/third_party/mesa3d/docs/relnotes/
D20.1.0.rst2645 - intel/dev: Split .num_subslices out of GEN12_FEATURES macro
D20.2.0.rst2849 - intel/dev: Split .num_subslices out of GEN12_FEATURES macro